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IDT74FCT162511CTPV

Description
Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, SSOP-56
Categorylogic    logic   
File Size115KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74FCT162511CTPV Overview

Registered Bus Transceiver, FCT Series, 1-Func, 16-Bit, True Output, CMOS, PDSO56, SSOP-56

IDT74FCT162511CTPV Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeSSOP
package instructionSSOP-56
Contacts56
Reach Compliance Codenot_compliant
Other featuresINDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION/ERROR DETECTION A TO B
Control typeINDEPENDENT CONTROL
Counting directionBIDIRECTIONAL
seriesFCT
JESD-30 codeR-PDSO-G56
JESD-609 codee0
length18.415 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeREGISTERED BUS TRANSCEIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits16
Number of functions1
Number of ports2
Number of terminals56
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE WITH SERIES RESISTOR
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Encapsulate equivalent codeSSOP56,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)225
power supply5 V
Prop。Delay @ Nom-Sup4.2 ns
propagation delay (tpd)5.3 ns
Certification statusNot Qualified
Maximum seat height2.794 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
translateN/A
Trigger typePOSITIVE EDGE
width7.5 mm
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
FEATURES:
0.5 MICRON CMOS Technology
Typical t
sk(o)
(Output Skew) < 250ps, clocked mode
Low input and output leakage
1µA (max)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V ±10%
Balanced Output Drivers:
– ±24mA (industrial)
– ±16mA (military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
DESCRIPTION:
The FCT162511T 16-bit registered/latched transceiver with parity is built
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the
OExx
control
pins allowing the designer to disable the error flag during combinational
transitions.
The control pins LEAB, CLKAB, and
OEAB
control operation in the A-to-B
direction while LEBA, CLKBA, and
OEBA
control the B-to-A direction.
GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
FUNCTIONAL BLOCK DIAGRAM
LEA B
CLKAB
Data
16
Parity
GEN/CHK
Byte
Parity
Generator/
Checker
2
Latch/
Register
PERB
(Open Drain)
Parity, data
18
OEAB
B0-15
PB1,2
A0-15
PA1,2
ODD/EVEN
LEB A
CLKB A
Parity, data
18
OEBA
Latch/
Register
Byte
Parity
Checking
Parity, Data
18
PERA
(Open Drain)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2001 Integrated Device Technology, Inc.
MAY 2001
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