IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS 16-BIT
IDT54/74FCT162511AT/CT
REGISTERED/LATCHED
TRANSCEIVER WITH PARITY
FEATURES:
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Typical t
sk(o)
(Output Skew) < 250ps, clocked mode
Low input and output leakage
≤
1µA (max)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V ±10%
Balanced Output Drivers:
– ±24mA (industrial)
– ±16mA (military)
Series current limiting resistors
Generate/Check, Check/Check modes
Open drain parity error allows wire-OR
Available in the following packages:
– Industrial: SSOP, TSSOP
– Military: CERPACK
DESCRIPTION:
The FCT162511T 16-bit registered/latched transceiver with parity is built
using advanced dual metal CMOS technology. This high-speed, low-power
transceiver combines D-type latches and D-type flip-flops to allow data flow in
transparent, latched, or clocked modes. The device has a parity generator/
checker in the A-to-B direction and a parity checker in the B-to-A direction. Error
checking is done at the byte level with separate parity bits for each byte. Separate
error flags exits for each direction with a single error flag indicating an error for
either byte in the A-to-B direction and a second error flag indicating an error for
either byte in the B-to-A direction. The parity error flags are open drain outputs
which can be tied together and/or tied with flags from other devices to form a single
error flag or interrupt. The parity error flags are enabled by the
OExx
control
pins allowing the designer to disable the error flag during combinational
transitions.
The control pins LEAB, CLKAB, and
OEAB
control operation in the A-to-B
direction while LEBA, CLKBA, and
OEBA
control the B-to-A direction.
GEN/
CHK is only for the selection of A-to-B operation. The B-to-A direction is always
in checking mode. The ODD/EVEN select is common between the two directions.
Except for the ODD/EVEN control, independent operation can be achieved
between the two directions by using the corresponding control lines.
FUNCTIONAL BLOCK DIAGRAM
LEA B
CLKAB
Data
16
Parity
GEN/CHK
Byte
Parity
Generator/
Checker
2
Latch/
Register
PERB
(Open Drain)
Parity, data
18
OEAB
B0-15
PB1,2
A0-15
PA1,2
ODD/EVEN
LEB A
CLKB A
Parity, data
18
OEBA
Latch/
Register
Byte
Parity
Checking
Parity, Data
18
PERA
(Open Drain)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2001 Integrated Device Technology, Inc.
MAY 2001
DSC-2916/-
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
BLOCK DIAGRAM
ODD/EVEN
OEAB
LEBA
CLKB A
CLKA B
LEA B
C
A
0
- A
7
D
C
C
D
OEBA
D
C
D
B
0
- B
7
P
O
C
D
C
D
P
C
D
C
D
PB
1
PA
1
I
C
A
8
- A
15
D
C
C
D
B
8
- B
15
C
D
D
P
O
C
D
C
D
C
D
C
D
PB
2
PA
2
I
C
GEN/CHK
D
C
PER A
(Open Drain)
D
C
D
PERB
(Open Drain)
C
D
P
2
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEAB
LEAB
PA
1
GND
A
0
A
1
V
CC
A
2
A
3
A
4
A
5
A
6
A
7
GND
PERA
A
8
A
9
A
10
A
11
A
12
A
13
V
CC
A
14
A
15
GND
PA
2
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GEN/CHK
CLKAB
PB
1
GND
B
0
B
1
V
CC
B
2
B
3
B
4
B
5
B
6
B
7
PERB
GND
B
8
B
9
B
10
B
11
B
12
B
13
V
CC
B
14
B
15
GND
PB
2
CLKBA
ODD/EVEN
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
Storage Temperature
DC Output Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
I/O
C
O
Parameter
(1)
Input Capacitance
I/O Capacitance
Open Drain
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
3.5
Max.
6
8
6
Unit
pF
pF
pF
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
PERA
PERB
PAx
(1)
PBx
ODD/EVEN
GEN/CHK
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Parity Mode Selection Input
A to B Port Generate or Check Mode Input
SSOP/ TSSOP/ CERPACK
TOP VIEW
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
3
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(1, 4)
Inputs
OEAB
H
L
L
L
L
L
L
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
L
H
Ax
X
L
H
L
H
X
X
Outputs
Bx
Z
L
H
L
H
B
(2)
B
(3)
FUNCTION TABLE
(PARITY CHECKING)
(1, 2, 3, 4)
A
0
– A
7
and P
A1(5)
Number of inputs that are high
1, 3, 5, 7 or 9
1, 3, 5, 7 or 9
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/EVEN
L
H
L
H
PERB
L
H
(6)
H
(6)
L
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is
and CLKBA.
2. Output level before the indicated steady-state
3. Output level before the indicated steady-state
provided that CLKAB was HIGH before LEAB
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑
= LOW-to-HIGH Transition
similar but uses
OEBA,
LEBA,
input conditions were established.
input conditions were established,
went LOW.
NOTES:
1. Conditions shown are for
GEN/CHK
= H,
OEAB
= L,
OEBA
= H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses
OEBA
= L,
OEAB
= H and errors will be indicated on
PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the
corresponding data regardless of parity errors (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
clock.
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag
PERB
is a combined flag for both bytes A0–A7 and A8–A15. If a parity
error occurs on either byte
PERB
will go low.
PERB
is an open drain output which must
be externally pulled up to achieve a logic HIGH.
FUNCTION TABLE
(PARITY GENERATION)
(1, 2, 3, 4, 5)
A0 – A7
Number of inputs that are high
1, 3, 5 or 7
1, 3, 5 or 7
0, 2, 4, 6 or 8
0, 2, 4, 6 or 8
ODD/EVEN
L
H
L
H
PB1
H
L
L
H
NOTES:
1. Conditions shown are for
GEN/CHK
= L,
OEAB
= L,
OEBA
= H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
triggered clock.
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
the parity on PB2.
5. The error flag
PERB
will remain in a high state during parity generation.
4
IDT54/74FCT162511AT/CT
FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
I
IL
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
I
OFF
V
OH
V
OL
Output LOW
Current
Output HIGH Current
Output Power Off Leakage Current
(Open Drain)
(5)
Output HIGH Voltage (I/O pins)
Output LOW
Voltage
(Open Drain)
(I/O pins)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –16mA MIL
I
OH
= –24mA IND
I
OL
= 16mA MIL
I
OL
= 24mA IND
I
OL
= 48mA MIL
I
OL
= 64mA IND
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ±5µA at T
A
= –55°C.
Parameter
(I/O pins)
(Open Drain)
Test Conditions
(1)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
V
CC
= 0, V
O
≤
5.5V
Min.
60
—
–60
—
2.4
—
—
Typ.
(2)
115
250
–115
—
3.3
0.3
0.3
Max.
200
—
–200
±1
—
0.55
0.55
Unit
mA
mA
mA
µA
V
V
V
5
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