70V9159L9PFG8 datasheet, PDF - EEWORLD Datasheet

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70V9159L9PFG8: DescriptionDual-Port SRAM, 8KX9, 9ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100; Categorystorage storage; File Size691KB，16 Pages; ManufacturerIDT (Integrated Device Technology)

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70V9159L9PFG8 Overview

Dual-Port SRAM, 8KX9, 9ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100

70V9159L9PFG8 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	QFP,
Reach Compliance Code	compliant
Maximum access time	9 ns
Other features	PIPELINED OR FLOW THROUGH ARCHITECTURE
JESD-30 code	S-PQFP-G100
memory density	73728 bit
Memory IC Type	DUAL-PORT SRAM
memory width	9
Number of functions	1
Number of terminals	100
word count	8192 words
character code	8000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8KX9
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Package shape	SQUARE
Package form	FLATPACK
Parallel/Serial	PARALLEL
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal location	QUAD

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HIGH-SPEED 3.3V 16/8K X 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features:

◆

IDT70V9169/59L

◆

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 6.5/7.5/9ns (max.)

– Industrial: 7.5ns (max.)

Low-power operation

– IDT70V916/59L/59L

Active: 450mW (typ.)

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the

FT/PIPE

pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Full synchronous operation on both ports

– 3.5ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

LVTTL- compatible, single 3.3V (±0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for 83 MHz

Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-

pin fine pitch Ball Grid Array (fpBGA) packages.

Functional Block Diagram

R/W

0/1

FT/PIPE

0/1

FT/PIPE

I/O

- I/O

I/O

- I/O

I/O

Control

I/O

Control

13L

(1)

CLK

ADS

CNTEN

CNTRST

NOTE:

1. A

is a NC for IDT70V9159.

13R

(1)

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

CLK

ADS

CNTEN

CNTRST

5655 drw 01

JUNE 2015

DSC-5655/4

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