DISCRETE SEMICONDUCTORS
DATA SHEET
BSS92
P-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of April 1995
File under Discrete Semiconductors, SC13b
1997 Jun 19
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL, etc.
•
High-speed switching
•
No secondary breakdown.
APPLICATIONS
•
Line current interrupter in telephony applications
•
Relay, high speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a TO-92 (SOT54) variant package.
handbook, halfpage
BSS92
PINNING - TO-92 (SOT54) variant
PIN
1
2
3
SYMBOL
g
d
s
DESCRIPTION
gate
drain
source
d
1
2
3
g
MAM144
s
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
V
GSO
I
D
R
DSon
P
tot
y
fs
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
drain-source on-state resistance
total power dissipation
forward transfer admittance
I
D
=
−100
mA; V
GS
=
−10
V
T
amb
≤
25
°C
V
DS
=
−25
V; I
D
=
−100
mA
open drain
CONDITIONS
MIN.
−
−
−
−
−
60
TYP.
−
−
−
10
−
200
MAX.
−240
±20
−150
20
1
−
V
V
mA
Ω
W
mS
UNIT
1997 Jun 19
2
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
operating junction temperature
T
amb
≤
25
°C;
note 1
open drain
CONDITIONS
−
−
−
−
−
−55
−
MIN.
BSS92
MAX.
−240
±20
−150
−600
1
+150
150
V
V
UNIT
mA
mA
W
°C
°C
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
PARAMETER
thermal resistance from junction to ambient
note 1
CONDITIONS
VALUE
125
UNIT
K/W
Note to the Limiting values and Thermal characteristics
1. Device mounted on a printed-circuit board, maximum lead length 4 mm; mounting pad for drain lead minimum
10 mm
×
10 mm.
CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
y
fs
C
iss
C
oss
C
rss
t
on
t
off
PARAMETER
drain-source breakdown voltage
gate-source threshold voltage
drain-source leakage current
gate leakage current
drain-source on-state resistance
forward transfer admittance
input capacitance
output capacitance
reverse transfer capacitance
CONDITIONS
V
GS
= 0; I
D
=
−250 µA
V
DS
= V
GS
; I
D
=
−1
mA
V
GS
= 0; V
DS
=
−60
V
V
GS
= 0; V
DS
=
−200
V
V
DS
= 0; V
GS
=
±20
V
V
GS
=
−10
V; I
D
=
−100
mA
V
DS
=
−25
V; I
D
=
−100
mA
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
V
GS
= 0; V
DS
=
−25
V; f = 1 MHz
V
GS
= 0 to
−10
V; V
DD
=
−50
V;
I
D
=
−250
mA
V
GS
=
−10
to 0 V; V
DD
=
−50
V;
I
D
=
−250
mA
MIN.
−240
−0.8
−
−
−
−
60
−
−
−
−
−
TYP.
−
−
−
−
−
10
200
65
20
6
MAX. UNIT
−
−2.8
−200
−60
±100
20
−
−
−
−
−
−
V
V
nA
µA
nA
Ω
mS
pF
pF
pF
Switching times
(see Figs 2 and 3)
turn-on time
turn-off time
5
20
ns
ns
1997 Jun 19
3
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSS92
handbook, halfpage
handbook, halfpage
10 %
VDD =
−50
V
INPUT
90 %
0
−10
V
50
Ω
ID
10 %
OUTPUT
90 %
MBB689
t on
t off
MBB690
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
1997 Jun 19
4
Philips Semiconductors
Product specification
P-channel enhancement mode
vertical D-MOS transistor
PACKAGE OUTLINE
Plastic single-ended leaded (through hole) package; 3 leads (on-circle)
BSS92
SOT54 variant
c
L2
E
d
A
L
b
1
2
D
e1
e
3
b
1
L1
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
5.2
5.0
b
0.48
0.40
b1
0.66
0.56
c
0.45
0.40
D
4.8
4.4
d
1.7
1.4
E
4.2
3.6
e
2.54
e1
1.27
L
14.5
12.7
L1
(1)
max
2.5
L2
max
2.5
Notes
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.
OUTLINE
VERSION
SOT54 variant
REFERENCES
IEC
JEDEC
TO-92
EIAJ
SC-43
EUROPEAN
PROJECTION
ISSUE DATE
97-04-14
1997 Jun 19
5
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