IR3502
DATA SHEET
XPHASE3
TM
CONTROL IC
DESCRIPTION
The IR3502 control IC combined with an
XPHASE3
Phase IC provides a full featured and flexible way to
implement a complete VR11.0 and VR11.1 power solution. The IR3502 provides overall system control
TM
and interfaces with any number of Phase ICs, each driving and monitoring a single phase. The XPhase3
architecture results in a power supply that is smaller, less expensive, and easier to design while providing
higher efficiency than conventional approaches.
TM
FEATURES
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1 to X phase operation with matching Phase IC
0.5% overall system set point accuracy
Daisy-chain digital phase timing provides accurate phase interleaving without external components
Programmable 250kHz to 9MHz clock oscillator frequency provides per phase switching frequency of
250kHz to 1.5MHz
Programmable Dynamic VID Slew Rate
Programmable VID Offset or No Offset
Programmable Load Line Output Impedance
High speed error amplifier with wide bandwidth of 30MHz and fast slew rate of 10V/us
Programmable constant converter output current limit during soft start
Hiccup over current protection with delay during normal operation
Central over voltage detection and latch with programmable threshold and communication to phase ICs
Over voltage signal output to system with overvoltage detection during powerup and normal operation
Load current reporting
Single NTC thermistor compensation for correct current reporting, OC Threshold, and Droop
Detection and protection of open remote sense line
Open control loop protection
IC bias linear regulator controller
Programmable VRHOT function monitors temperature of power stage through a NTC thermistor
Remote sense amplifier with true converter voltage sensing
Simplified VR Ready (VRRDY) output provides indication of proper operation
Small thermally enhanced 32L 5mm x 5mm MLPQ package
RoHS compliant
ORDERING INFORMATION
Device
IR3502MTRPBF
* IR3502MPBF
•
Samples only
Package
32 Lead MLPQ
(5 x 5 mm body)
32 Lead MLPQ
(5 x 5 mm body)
Order Quantity
3000 per reel
100 piece strips
Page 1 of 39
July 28, 2009
IR3502
APPLICATION CIRCUIT
32
31
30
29
28
27
26
25
32
31
30
29
28
27
26
PHSOUT
25
CLKOUT
VCCLDRV
VCCLDRV
VIDSEL
VCCL
VRRDY
VCCLFB
PHSOUT
VRRDY
PHSIN
VCCL
CLKOUT
1
2
3
4
5
6
7
8
VID7
VID6
VID5
VID4
VID3
VID2
VID1
LGND
24
23
22
21
20
19
18
17
PHSIN
IMON
IIN
1
2
3
4
5
6
7
8
VID7
VID6
VID5
VID4
VID3
VID2
VID1
GND
ROSC
24
23
22
21
20
19
18
17
ROSC / OVP
SS/DEL
SS/DEL
IR3500
VDAC
OCSET
VSETPT
IIN
IR3502
VDAC
VSETPT
VDAC_BUFF
VN
HOTSET
VOSEN+
VOSEN+
ENABLE
ENABLE
VOSEN-
VOSEN-
VRHOT
VRHOT
EAOUT
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
Figure 1 – PIN difference between IR3500 and IR3502
16
EAOUT
VID0
VDRP
VID0
HOTSET
VDRP
VO
VO
FB
FB
+12V
Q2
12V
VCCL
CVCCL
RVCCLDRV
IIN
PHSIN
VRRDY
IOUT
32
30
29
28
27
26
PHSOUT
RMON
CLKOUT
31
25
CLKOUT
CMON
VRRDY
VCCLDRV
VCCL
IIN
PHSIN
IMON
VOSEN-
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1
2
3
4
5
6
7
8
VID7
VID6
VID5
VID4
VID3
VID2
VID1
PHSOUT
RMON1
GND
ROSC
24
23
22
21
20
19
18
17
ROSC
CSS/DEL
RVDAC
RVSETPT
RTCMP3
CVDAC
VDAC
SS/DEL
IR3502
VDAC
VSETPT
VDAC_BUFF
VN
HOTSET
VOSEN+
ENABLE
VOSEN-
VRHOT
EAOUT
VID0
VDRP
RTCMP1
RTHERM
VO
FB
10
11
12
13
14
15
ENABLE
VRHOT
16
RTCMP2
RDRP
RHOTSET1
RHOTSET3
9
CHOTSET
RFB1
RHOTSET2
RFB
CFB1
REA
CEA1
CEA
EAOUT
VOSEN+
VOSEN-
Figure 2 – IR3502 Application Circuit
Page 2 of 39
July 28, 2009
IR3502
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications are not implied.
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….-65 C to 150 C
ESD Rating………………………………………HBM Class 1C JEDEC Standard
MSL Rating………………………………………2
o
Reflow Temperature…………………………….260 C
o
PIN #
1-8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
VID7-0
ENABLE
VRHOT
HOTSET
VOSEN-
VOSEN+
VO
FB
EAOUT
VDRP
VN
VDAC_BUFF
VSETPT
VDAC
SS/DEL
ROSC/OVP
LGND
CLKOUT
PHSOUT
PHSIN
VCCL
IIN
VCCLDRV
VRRDY
IMON
V
MAX
7.5V
3.5V
7.5V
7.5V
1.0V
7.5V
7.5V
7.5V
7.5V
7.5V
7.5V
3.5V
3.5V
3.5V
7.5V
7.5V
n/a
7.5V
7.5V
7.5V
7.5V
7.5V
10V
VCCL + 0.3V
3.5V
V
MIN
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.5V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
I
SOURCE
1mA
1mA
1mA
1mA
5mA
5mA
35mA
1mA
35mA
35mA
1mA
1mA
1mA
1mA
1mA
1mA
20mA
100mA
10mA
1mA
1mA
1mA
1mA
1mA
25mA
I
SINK
1mA
1mA
50mA
1mA
1mA
1mA
5mA
1mA
5mA
1mA
1mA
35mA
1mA
1mA
1mA
1mA
1mA
100mA
10mA
1mA
20mA
1mA
50mA
20mA
1mA
Page 3 of 39
July 28, 2009
IR3502
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8V≤Vin≤16V, VCCL = 6.8V±3.4%, -0.3V
≤
VOSEN-
≤
o
o
0.3V, 0 C
≤
T
J
≤
100 C, 7.75K
≤
R
OSC
≤
50.0 K , C
SS/DEL
= 0.1µF +/-10%.
PARAMETER
VDAC Reference
System Set-Point Accuracy
TEST CONDITION
VID
≥
1V
0.8V
≤
VID < 1V
0.5V
≤
VID < 0.8V
VSETPT connected to VDAC
MIN
-0.5
-5
-8
30
500
-1
0.5
0.570
TYP
MAX
0.5
+5
+8
58
700
1
2.1
0.620
1
1
275
550
1.65
1
1
70
9
0.6
20
UNIT
%
mV
mV
µA
mV
µA
µs
V
V
V
kHz
kHz
MHz
V
V
%
mV
mA
mA
MHz
V/µs
10
15
0.5
7
mV
mA
mA
MHz
V/µs
67
mV
Source & Sink Currents
VIDx Input Threshold
VIDx Input Bias Current
0V≤V(VIDx)≤2.5V.
VIDx OFF State Blanking Delay Measure time till VRRDY drives low
Oscillator
ROSC Voltage
CLKOUT High Voltage
I(CLKOUT)= -10 mA, measure V(VCCL)
– V(CLKOUT).
CLKOUT Low Voltage
I(CLKOUT)= 10 mA
PHSOUT Frequency
R
OSC
= 50.0 K
PHSOUT Frequency
R
OSC
= 24.5 K
PHSOUT Frequency
R
OSC
= 7.75 K
PHSOUT High Voltage
I(PHSOUT)= -1 mA, measure V(VCCL)
– V(PHSOUT)
PHSOUT Low Voltage
I(PHSOUT)= 1 mA
PHSIN Threshold Voltage
Compare to V(VCCL)
VDAC Buffer Amplifier
Input Offset Voltage
V(VDAC_BUFF) – V(VDAC), 0.5V
≤
V(VDAC)
≤
1.6V, < 1mA load
Source Current
0.5V
≤
V(VDAC)
≤
1.6V
Sink Current
0.5V
≤
V(VDAC)
≤
1.6V
Unity Gain Bandwidth
Note 1
Slew Rate
Note 1
Thermal Compensation Amplifier
Output Offset Voltage
0V
≤
V(IIN) – V(VDAC)
≤
1.6V, 0.5V
≤
V(VDAC)
≤
1.6V, Req/R2 = 2
Source Current
0.5V
≤
V(VDAC)
≤
1.6V
Sink Current
0.5V
≤
V(VDAC)
≤
1.6V
Unity Gain Bandwidth
Note 1, Req/R2 = 2
Slew Rate
Note 1
Current Report Amplifier
Output Offset Voltage
V(VDRP)–V(VDAC) = 0,225,450,900mV
44
600
0
1.3
0.595
225
450
1.35
250
500
1.50
30
-5
0.3
3.5
50
0
0.44
13
3.5
1.5
0
8
0.4
4.5
5.5
52
-10
3
0.3
2
37
Page 4 of 39
July 28, 2009
IR3502
PARAMETER
TEST CONDITION
Source Current
0.5V
≤
V(IMON)
≤
0.9V
Sink Resistance
0.5V
≤
V(IMON)
≤
0.9V
Unity Gain Bandwidth
Note 1
Input Filter Time Constant
Max Output Voltage
Soft Start and Delay
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
VRRDY Delay (TD4 + TD5)
OC Delay Time
V(VDRP) – V(DACBUFF) = 1.67 mV
SS/DEL to FB Input Offset With FB = 0V, adjust V(SS/DEL) until
Voltage
EAOUT drives high
Charge Current
Discharge Current
Charge/Discharge Current Ratio
Charge Voltage
Relative to Charge Voltage, SS/DEL rising
Delay Comparator Threshold
Relative to Charge Voltage, SS/DEL falling
Delay Comparator Threshold
Delay Comparator Input Filter
Delay Comparator Hysteresis
VID Sample Delay Comparator
Threshold
Discharge Comp. Threshold
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Note 1
Input Offset Voltage
0.5V≤ V(VOSEN+) - V(VOSEN-)
≤
1.6V
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-)
≤
1.6V
Source Current
0.5V≤ V(VOSEN+) - V(VOSEN-)
≤
1.6V
Slew Rate
0.5V≤ V(VOSEN+) - V(VOSEN-)
≤
1.6V
VOSEN+ Bias Current
0.5 V < V(VOSEN+) < 1.6V
VOSEN- Bias Current
-0.3V
≤
VOSEN-
≤
0.3V, All VID Codes
High Voltage
V(VCCL) – V(VO)
Low Voltage
V(VCCL)=7V
Error Amplifier
Input Offset Voltage
Measure V(FB) – V(VSETPT). Note 2
FB Bias Current
VSETPT Bias Current
R
OSC
= 24.5 K
DC Gain
Note 1
Bandwidth
Note 1
Slew Rate
Note 1
Sink Current
Source Current
Maximum Voltage
Measure V(VCCL) – V(EAOUT)
Page 5 of 39
MIN
5
5
TYP
9
10
1
1
1.09
2.9
2.2
1.2
1.2
125
1.4
52.5
4.5
12
4.0
80
120
5
30
3.0
200
6.4
0
1
9
4
160
2
MAX
15
17
UNIT
mA
k
MHz
µs
V
ms
ms
ms
ms
us
V
µA
µA
µA/µA
V
mV
mV
µs
mV
V
mV
MHz
mV
mA
mA
V/us
µA
µA
V
mV
mV
µA
µA
dB
MHz
V/µs
mA
mA
mV
1.04
1.0
0.8
0.3
0.5
75
0.7
35.0
2.5
10
3.6
50
85
10
2.8
150
3.0
-3
0.4
3
2
1.145
3.5
3.25
3.0
2.3
300
1.9
70.0
6.5
16
4.2
125
160
60
3.2
275
9.0
3
2
20
8
100
275
2.5
50
1.5
-1
-1
23.00
100
20
7
0.40
5
500
0
1
0
1
24.25 25.50
110
120
30
40
12
20
0.85
1.00
8
12
780
950
July 28, 2009
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