PD - 94448A
AFL1203R3S
ADVANCED ANALOG
HIGH RELIABILITY
HYBRID DC/DC CONVERTER
Description
The AFL Series of DC/DC converters feature high power
density with no derating over the full military tempera-
ture range. This series is offered as part of a complete
family of converters providing single and dual output
voltages and operating from nominal +28 or +270 volt
inputs with output power ranging from 66 to 120 watts.
For applications requiring higher output power, multiple
converters can be operated in parallel. The internal cur-
rent sharing circuits assure equal current distribution
among the paralleled converters. This series incorpo-
rates Advanced Analog’s proprietary magnetic pulse
feedback technology providing optimum dynamic line
and load regulation response. This feedback system
samples the output voltage at the pulse width modulator
fixed clock frequency, nominally 550 KHz. Multiple con-
verters can be synchronized to a system clock in the
500 KHz to 700 KHz range or to the synchronization
output of one converter. Undervoltage lockout, primary
and secondary referenced inhibit, soft-start and load
fault protection are provided on all models.
These converters are hermetically packaged in two en-
closure variations, utilizing copper core pins to mini-
mize resistive DC losses. Three lead styles are avail-
able, each fabricated with Advanced Analog’s rugged
ceramic lead-to-package seal assuring long term
hermeticity in the most harsh environments.
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are available in four screening
grades to satisfy a wide range of requirements. The CH
grade is fully compliant to the requirements of MIL-PRF-
38534 for class H. The HB grade is fully processed and
screened to the class H requirement, but does not have
material element evaluated to the class H requirement.
Both grades are tested to meet the complete group “A”
test specification over the full military temperature range
without output power deration. Two grades with more
limited screening are also available for use in less de-
120V Input, 3.3V Output
AFL
Features
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80 To 160 Volt Input Range
3.3 Volt Output
High Power Density - 50 W / in3
66 Watt Output Power
Parallel Operation with Stress and Current
Sharing
Low Profile (0.380") Seam Welded Package
Ceramic Feedthru Copper Core Pins
High Efficiency - to 74%
Full Military Temperature Range
Continuous Short Circuit and Overload
Protection
Remote Sensing Terminals
Primary and Secondary Referenced
Inhibit Functions
Line Rejection > 50 dB - DC to 50KHz
External Synchronization Port
Fault Tolerant Design
Dual Output Versions Available
Standard Military Drawings Available
manding applications. Variations in electrical, me-
chanical and screening can be accommodated.
Contact Advanced Analog for special require-
ments.
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1
07/10/02
AFL1203R3S
Specifications
ABSOLUTE MAXIMUM RATINGS
Input Voltage
Soldering Temperature
Case Temperature
-0.5V to 180V
300°C for 10 seconds
Operating
Storage
-55°C to +125°C
-65°C to +135°C
Electrical Performance Characteristics
-55°C < T
CASE
< +125°C, 80V< V
IN
< 160V
unless otherwise specified.
Parameter
INPUT VOLTAGE
OUTPUT VOLTAGE
1
2, 3
OUTPUT CURRENT
OUTPUT POWER
MAXIMUM CAPACITIVE LOAD
OUTPUT VOLTAGE
TEMPERATURE COEFFICIENT
OUTPUT VOLTAGE REGULATION
Line
Load
OUTPUT RIPPLE VOLTAGE
1, 2, 3
INPUT CURRENT
No Load
Inhibit 1
Inhibit 2
INPUT RIPPLE CURRENT
1, 2, 3
CURRENT LIMIT POINT
Expressed as a Percentage
of Full Rated Load
LOAD FAULT POWER DISSIPATION
Overload or Short Circuit
EFFICIENCY
1, 2, 3
SWITCHING FREQUENCY
ISOLATION
MTBF
1, 2, 3
1
Input to Output or Any Pin to Case
(except Pin 3). Test @ 500VDC
MIL-HDBK-217F, AIF @ TC = 40°C
1
2
3
V
IN
= 120 Volts
1, 2, 3
V
IN
= 120 Volts, 100% Load
72
500
100
300
74
550
600
%
KHz
MΩ
KHrs
32
W
1
2, 3
1, 2, 3
1, 2, 3
4
VIN = 80, 120, 160 Volts, Note 6
Note 6
Note 1
VIN = 120 Volts, 100% Load - Note
1, 6
1, 2, 3
1, 2, 3
No Load, 50% Load, 100% Load
VIN = 80, 120, 160 Volts
VIN = 80, 120, 160 Volts, 100%
Load,
BW = 10MHz
VIN = 120 Volts
IOUT = 0
Pin 4 Shorted to Pin 2
Pin 12 Shorted to Pin 8
VIN = 120 Volts, 100% Load
B.W. = 10MHz
VOUT = 90% VNOM
Note 5
115
105
125
125
115
140
%
%
%
10,000
-0.015
+0.015
Group A
Subgroups
Note 6
VIN = 120 Volts, 100% Load
3.27
3.23
3.30
3.33
3.37
20
66
V
V
A
W
µfd
%/°C
Test Conditions
Min
80
Nom
120
Max
160
Unit
V
-10.0
-35.0
+10.0
+35.0
30
mV
mV
mVpp
30
40
3.0
5.0
60
mA
mA
mA
mA
mApp
For Notes to Specifications, refer to page 3
2
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AFL1203R3S
Elecrical Performance Characteristics
(Continued)
Parameter
ENABLE INPUTS
(Inhibit Function)
Converter Off
Sink Current
Converter On
Sink Current
SYNCHRONIZATION INPUT
Frequency Range
Pulse Amplitude, Hi
Pulse Amplitude, Lo
Pulse Rise Time
Pulse Duty Cycle
LOAD TRANSIENT RESPONSE
Amplitude
Recovery
Amplitude
Recovery
LINE TRANSIENT RESPONSE
Amplitude
Recovery
TURN-ON CHARACTERISTICS
Overshoot
Delay
LOAD FAULT RECOVERY
LINE REJECTION
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
Group A
Subgroups
1, 2, 3
1, 2, 3
Test Conditions
Logical Low, Pin 4 or Pin 12
Note 1
Logical High, Pin 4 and Pin 12 - Note 9
Note 1
Min
-0.5
2.0
Nom
Max
0.8
100
50
100
700
10
0.8
100
80
Unit
V
µA
V
µA
KHz
V
V
nSec
%
1, 2, 3
1, 2, 3
1, 2, 3
Note 1
Note 1
Note 2, 8
Load Step 50%
⇔
100%
Load Step 10%
⇔
50%
Note 1, 2, 3
VIN Step = 80
⇔
160 Volts
VIN = 80, 120, 160 Volts. Note 4
Enable 1, 2 on. (Pins 4, 12 high or open)
500
2.0
-0.5
20
-450
-450
450
200
450
400
mV
µSec
mV
µSec
-500
500
500
mV
µSec
50
Same as Turn On Characteristics.
MIL-STD-461, CS101, 30Hz to 50KHz
Note 1
50
75
250
120
mV
mSec
60
dB
Notes to Specifications:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Parameters not 100% tested but are guaranteed to the limits specified in the table.
Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within
±1%
of V
OUT
at 50% load.
Line transient transition time
≥
100
µSec.
Turn-on delay is measured with an input voltage rise time of between 100 and 500 volts per millisecond.
Current limit point is that condition of excess load causing output voltage to drop to 90% of nominal.
Parameter verified as part of another test.
All electrical tests are performed with the remote sense leads connected to the output leads at the load.
Load transient transition time
≥
10
µSec.
Enable inputs internally pulled high. Nominal open circuit voltage
≈
4.0VDC.
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3
AFL1203R3S
AFL120XXS Circuit Description
Figure I. AFL Single Output Block Diagram
DC INPUT
1
INPUT
FILTER
ENABLE 1
4
PRIMARY
BIAS SUPPLY
OUTPUT
FILTER
7
10
+ OUTPUT
+ SENSE
CURRENT
SENSE
SYNC OUTPUT
5
SHARE
CONTROL
SYNC INPUT
6
.*
ERROR
AMP
& REF
AMPLIFIER
11
12
SHARE
ENABLE 2
CASE
3
SENSE
AMPLIFIER
9
8
- SENSE
OUTPUT RETURN
INPUT RETURN
2
Circuit Operation and Application Information
The AFL series of converters employ a forward switched
mode converter topology. (refer to Figure I.) Operation of
the device is initiated when a DC voltage whose magnitude
is within the specified input limits is applied between pins 1
and 2. If pin 4 is enabled (at a logical 1 or open) the primary
bias supply will begin generating a regulated housekeeping
voltage bringing the circuitry on the primary side of the con-
verter to life. Two power MOSFETs used to chop the DC
input voltage into a high frequency square wave, apply this
chopped voltage to the power transformer. As this switch-
ing is initiated, a voltage is impressed on a second winding
of the power transformer which is then rectified and applied
to the primary bias supply. When this occurs, the input
voltage is shut out and the primary bias voltage becomes
exclusively internally generated.
The switched voltage impressed on the secondary output
transformer winding is rectified and filtered to provide the
converter output voltage. An error amplifier on the second-
ary side compares the output voltage to a precision refer-
ence and generates an error signal proportional to the dif-
ference. This error signal is magnetically coupled through
the feedback transformer into the controller section of the
converter varying the pulse width of the square wave sig-
nal driving the MOSFETs, narrowing the width if the output
voltage is too high and widening it if it is too low.
the sense leads should be connected to their respective
output terminals at the converter. Figure III. illustrates a
typical application.
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing TTL compatible, positive logic signals
to either of two enable pins (pin 4 or 12). The distinction
between these two signal ports is that enable 1 (pin 4) is
referenced to the input return (pin 2) while enable 2 (pin 12)
is referenced to the output return (pin 8). Thus, the user
has access to an inhibit function on either side of the isola-
tion barrier. Each port is internally pulled “high” so that
when not used, an open connection on both enable pins
permits normal converter operation. When their use is
desired, a logical “low” on either port will shut the con-
verter down.
Figure II. Enable Input Equivalent Circuit
+5.6V
100K
Pin 4 or
Pin 12
1N4148
290K
Disable
Remote Sensing
Connection of the
+
and
-
sense leads at a remotely locat-
led load permits compensation for resistive voltage drop
between the converter output and the load when they are
physically separated by a significant distance. This con-
nection allows regulation to the placard voltage at the point
of application.When the remote sensing features is not used,
2N3904
150K
Pin 2 or
Pin 8
4
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AFL1203R3S
Internally, these ports differ slightly in their function. In use,
a low on Enable 1 completely shuts down all circuits in the
converter while a low on Enable 2 shuts down the second-
ary side while altering the controller duty cycle to near zero.
Externally, the use of either port is transparent to the user
save for minor differences in idle current. (See specification
table).
high
l
evel of +2.0 volts. The sync output of another con-
verter which has been designated as the master oscillator
provides a convenient frequency source for this mode of
operation. When external synchronization is not required,
the sync in pin should be left unconnected thereby permit-
ting the converter to operate at its’ own internally set fre-
quency.
The sync output signal is a continuous pulse train set at
550
±50
KHz, with a duty cycle of 15
±5%.
This signal is
referenced to the input return and has been tailored to be
compatible with the AFL sync input port. Transition times
are less than 100 ns and the low level output impedance is
less than 50 ohms. This signal is active when the DC input
voltage is within the specified operating range and the con-
verter is not inhibited. This output has adequate drive re-
serve to synchronize at least five additional converters. A
typical synchronization connection option is illustrated in
Figure III.
Synchronization of Multiple Converters
When operating multiple converters, system requirements
often dictate operation of the converters at a common fre-
quency. To accommodate this requirement, the AFL series
converters provide both a synchronization input and out-
put.
The sync input port permits synchronization of an AFL co-
nverter to any compatible external frequency source oper-
ating between 500 and 700 KHz. This input signal should
be referenced to the input return and have a 10% to 90%
duty cycle. Compatibility requires transition times less th
an100 ns, maximum low level of +0.8 volts and a minimum
Figure III. Preferred Connection for Parallel Operation
Power
Input
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
Optional
Synchronization
Connection
6
Share Bus
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
6
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
to Load
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
6
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
(Other Converters)
Parallel Operation-Current and Stress Sharing
Figure III. illustrates the preferred connection scheme for
operation of a set of AFL converters with outputs operating
in parallel. Use of this connection permits equal sharing of
a load current exceeding the capacity of an individual AFL
among the members of the set. An important feature of the
AFL series operating in the parallel mode is that in addition
to sharing the current, the stress induced by temperature
will also be shared. Thus if one member of a paralleled set
is operating at a higher case temperture, the current it pro-
vides to the load will be reduced as compensation for the
temperature induced stress on that device.
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