PD - 96224
Applications
l
DC Motor Drive
l
High Efficiency Synchronous Rectification in SMPS
l
Uninterruptible Power Supply
l
High Speed Power Switching
l
Hard Switched and High Frequency Circuits
G
IRLR3636PbF
IRLU3636PbF
HEXFET
®
Power MOSFET
D
Benefits
l
Optimized for Logic Level Drive
l
Very Low R
DS(ON)
at 4.5V V
GS
l
Superior R*Q at 4.5V V
GS
l
Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l
Fully Characterized Capacitance and Avalanche
SOA
l
Enhanced body diode dV/dt and dI/dt Capability
l
Lead-Free
G
S
V
DSS
R
DS(on)
typ.
max.
I
D (Silicon Limited)
I
D (Package Limited)
D
60V
5.4m
:
6.8m
:
99A
50A
c
S
G
S
D
G
D-Pak
I-Pak
IRLR3636PbF IRLU3636PbF
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
I
D
@ T
C
= 25°C
I
D
@ T
C
= 100°C
I
D
@ T
C
= 25°C
I
DM
P
D
@T
C
= 25°C
V
GS
dv/dt
T
J
T
STG
Parameter
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Silicon Limited)
Continuous Drain Current, V
GS
@ 10V (Package Limited)
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
99
70
50
396
143
0.95
±16
22
c
c
Units
A
d
W
W/°C
V
V/ns
°C
f
-55 to + 175
300 (1.6mm from case)
170
See Fig.14, 15, 22a, 22b
Avalanche Characteristics
E
AS (Thermally limited)
I
AR
E
AR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
e
d
j
mJ
A
mJ
Thermal Resistance
Symbol
R
θJC
R
θJA
R
θJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
Junction-to-Ambient
k
Parameter
Typ.
–––
–––
–––
Max.
1.05
50
110
Units
°C/W
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1
02/06/09
IRLR/U3636PbF
Static @ T
J
= 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
60
–––
–––
–––
1.0
–––
–––
–––
–––
–––
Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage
∆V
(BR)DSS
/∆T
J
Breakdown Voltage Temp. Coefficient
R
DS(on)
V
GS(th)
I
DSS
I
GSS
R
G(int)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
–––
0.07
5.4
6.6
–––
–––
–––
–––
–––
0.6
–––
V V
GS
= 0V, I
D
= 250µA
––– V/°C Reference to 25°C, I
D
= 5mA
6.8
V
GS
= 10V, I
D
= 50A
mΩ
8.3
V
GS
= 4.5V, I
D
= 50A
2.5
V V
DS
= V
GS
, I
D
= 100µA
V
DS
= 60V, V
GS
= 0V
20
µA
250
V
DS
= 60V, V
GS
= 0V, T
J
= 125°C
V
GS
= 16V
100
nA
-100
V
GS
= -16V
g
g
d
–––
Ω
Dynamic @ T
J
= 25°C (unless otherwise specified)
Symbol
gfs
Q
g
Q
gs
Q
gd
Q
sync
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
C
oss
eff. (ER)
C
oss
eff. (TR)
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Q
g
- Q
gd
)
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min. Typ. Max. Units
31
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
33
11
15
18
45
216
43
69
3779
332
163
437
636
–––
49
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
Conditions
Effective Output Capacitance (Energy Related)
Effective Output Capacitance (Time Related)
iÃ
h
V
DS
= 25V, I
D
= 50A
I
D
= 50A
V
DS
= 30V
nC
V
GS
= 4.5V
I
D
= 50A, V
DS
=0V, V
GS
= 4.5V
V
DD
= 39V
I
D
= 50A
ns
R
G
= 7.5
Ω
V
GS
= 4.5V
V
GS
= 0V
V
DS
= 50V
pF ƒ = 1.0MHz
V
GS
= 0V, V
DS
= 0V to 48V ,See Fig.11
V
GS
= 0V, V
DS
= 0V to 48V
g
g
i
h
Diode Characteristics
Symbol
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
t
on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Min. Typ. Max. Units
–––
–––
–––
–––
99
Conditions
MOSFET symbol
D
A
Ãd
396
showing the
integral reverse
G
S
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
––– –––
1.3
V
–––
27
–––
ns
–––
32
–––
–––
31
–––
nC
T
J
= 125°C
–––
43
–––
–––
2.1
–––
A T
J
= 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode.
T
J
= 25°C, I
S
= 50A, V
GS
= 0V
V
R
= 51V,
T
J
= 25°C
T
J
= 125°C
I
F
= 50A
di/dt = 100A/µs
T
J
= 25°C
g
g
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 50A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by T
Jmax
, starting T
J
= 25°C, L = 0.136 mH
R
G
= 25Ω, I
AS
= 50A, V
GS
=10V. Part not recommended for use
above this value .
I
SD
≤
50A, di/dt
≤
1109 A/µs, V
DD
≤
V
(BR)DSS
, T
J
≤
175°C.
Pulse width
≤
400µs; duty cycle
≤
2%.
C
oss
eff. (TR) is a fixed capacitance that gives the same charging time
as C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
C
oss
eff. (ER) is a fixed capacitance that gives the same energy as
C
oss
while V
DS
is rising from 0 to 80% V
DSS
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniquea refer to applocation
note # AN- 994 echniques refer to application note #AN-994.
R
θ
is measured at T
J
approximately 90°C.
2
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IRLR/U3636PbF
1000
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
1000
TOP
VGS
15V
10V
4.5V
4.0V
3.5V
3.3V
3.0V
2.7V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
10
2.7V
1
2.7V
≤
60µs PULSE WIDTH
Tj = 25°C
≤
60µs PULSE WIDTH
Tj = 175°C
1
0.1
1
10
100
0.1
0.1
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
Fig 2.
Typical Output Characteristics
2.5
ID = 50A
VGS = 10V
2.0
ID, Drain-to-Source Current (A)
100
T J = 175°C
T J = 25°C
10
1.5
1
VDS = 25V
≤60µs
PULSE WIDTH
0.1
1
2
3
4
5
6
7
1.0
0.5
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
100000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
Fig 4.
Normalized On-Resistance vs. Temperature
5.0
4.5
VGS, Gate-to-Source Voltage (V)
ID= 50A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VDS= 48V
VDS= 30V
VDS= 12V
C, Capacitance (pF)
10000
Ciss
1000
Coss
Crss
100
1
10
VDS, Drain-to-Source Voltage (V)
100
0.0
0
5
10
15
20
25
30
35
40
QG, Total Gate Charge (nC)
Fig 5.
Typical Capacitance vs. Drain-to-Source Voltage
Fig 6.
Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRLR/U3636PbF
1000
1000
OPERATION IN THIS AREA LIMITED BY R (on)
DS
100
T J = 175°C
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
100µsec
10
T J = 25°C
10
LIMITED BY PACKAGE
1msec
10msec
1
VGS = 0V
0.1
0.1
0.4
0.7
1
1.3
1.6
1.9
VSD, Source-to-Drain Voltage (V)
1
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
1
10
DC
0.1
100
VDS, Drain-to-Source Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
Fig 8.
Maximum Safe Operating Area
80
Id = 5mA
75
70
65
60
55
50
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
110
100
90
Limited By Package
ID, Drain Current (A)
80
70
60
50
40
30
20
10
0
25
50
75
100
125
150
175
T C , Case Temperature (°C)
Fig 9.
Maximum Drain Current vs.
Case Temperature
0.8
Fig 10.
Drain-to-Source Breakdown Voltage
800
EAS , Single Pulse Avalanche Energy (mJ)
700
600
500
400
300
200
100
0
0.6
ID
TOP
5.69A
10.64A
BOTTOM 50A
Energy (µJ)
0.4
0.2
0.0
0
5 10 15 20 25 30 35 40 45 50 55 60 65
VDS, Drain-to-Source Voltage (V)
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 11.
Typical C
OSS
Stored Energy
Fig 12.
Maximum Avalanche Energy vs. DrainCurrent
4
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IRLR/U3636PbF
10
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
( THERMAL RESPONSE )
0.1
τ
J
R
1
R
1
τ
J
τ
1
τ
2
R
2
R
2
R
3
R
3
τ
3
R
4
R
4
τ
C
τ
τ
4
Ri (°C/W)
0.02028
0.29406
0.49179
0.24336
τi
(sec)
0.000011
0.000158
0.001393
0.00725
τ
1
τ
2
τ
3
τ
4
0.01
Ci=
τi/Ri
Ci i/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
0.01
0.1
0.001
1E-006
1E-005
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 13.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01
10
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj
= 150°C and
Tstart =25°C (Single Pulse)
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ
j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
tav (sec)
1.0E-03
1.0E-02
1.0E-01
Fig 14.
Typical Avalanche Current vs.Pulsewidth
200
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 50A
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of T
jmax
. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asT
jmax
is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. P
D (ave)
= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. I
av
= Allowable avalanche current.
7.
∆T
=
Allowable rise in junction temperature, not to exceed T
jmax
(assumed as
25°C in Figure 14, 15).
t
av =
Average time in avalanche.
D = Duty cycle in avalanche = t
av
·f
Z
thJC
(D, t
av
) = Transient thermal resistance, see Figures 13)
175
EAR , Avalanche Energy (mJ)
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
P
D (ave)
= 1/2 ( 1.3·BV·I
av
) =
DT/
Z
thJC
I
av
= 2DT/ [1.3·BV·Z
th
]
E
AS (AR)
= P
D (ave)
·t
av
Fig 15.
Maximum Avalanche Energy vs. Temperature
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