Preliminary
GS880F18/36T-11/11.5/12/14/18
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• Flow Through mode operation
• 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• 100-lead TQFP package
-11
-11.5
-12
-14
-18
Flow
t
KQ
11 ns 11.5 ns 12 ns
14 ns
18 ns
15 ns
15 ns
15 ns
20 ns
Through tCycle 15 ns
2-1-1-1
I
DD
180 mA 180 mA 180 mA 175 mA 165 mA
512K x 18, 256K x 36
8Mb Sync Burst SRAMs
11 ns–18 ns
3.3 V V
DD
3.3 V and 2.5 V I/O
RAMS should be designed with V
SS
connected to the FT pin
location to ensure the broadest access to multiple vendor
sources. Boards designed with FT pin pads tied low may be
stuffed with GSI’s Pipeline/Flow Through-configurable Burst
RAMS or any vendor’s Flow Through or configurable Burst
SRAM. Bumps designed with the FT pin location tied high or
floating must employ a non-configurable Flow Through Burst
RAM, like this RAM, to achieve flow through functionality.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the byte write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(high) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
Functional Description
Applications
The GS880F18/36T is a 9,437,184-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
The GS880F18/36T operates on a 3.3 V power supply, and all
inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate
output power (V
DDQ
) pins are used to decouple output noise
from the internal circuit.
Controls
Addresses, data I/Os, chip enables (E1, E2, E3), address burst
control inputs (ADSP, ADSC, ADV) and write control inputs
(Bx, BW, GW) are synchronous and are controlled by a
positive-edge-triggered clock input (CK). Output enable (G)
and power down control (ZZ) are asynchronous inputs. Burst
cycles can be initiated with either ADSP or ADSC inputs. In
Burst mode, subsequent burst addresses are generated
internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or
interleave order with the Linear Burst Order (LBO) input. The
Burst function need not be used. New addresses can be loaded
on every cycle with no degradation of chip performance.
Designing For Compatibility
The JEDEC Standard for Burst RAMS calls for a FT mode pin
option (pin 14 on TQFP). Board sites for flow through Burst
Rev: 1.06 9/2000
1/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F18 100-Pin TQFP Pinout
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B1
DQ
B2
V
SS
V
DDQ
DQ
B3
DQ
B4
NC
V
DD
NC
V
SS
DQ
B5
DQ
B6
V
DDQ
V
SS
DQ
B7
DQ
B8
DQ
B9
NC
V
SS
V
DDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
512K x 18
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
NC
NC
B
B
B
A
E
3
V
DD
V
SS
A
18
NC
NC
V
DDQ
V
SS
NC
DQ
A9
DQ
A8
DQ
A7
V
SS
V
DDQ
DQ
A6
DQ
A5
V
SS
NC
V
DD
ZZ
DQ
A4
DQ
A3
V
DDQ
V
SS
DQ
A2
DQ
A1
NC
NC
V
SS
V
DDQ
NC
NC
NC
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
A
17
A
10
A
11
A
12
A
13
A
14
A
15
2/22
Rev: 1.06 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
16
© 2000, Giga Semiconductor, Inc.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F36 100-Pin TQFP Pinout
DQ
C9
DQ
C8
DQ
C7
V
DDQ
V
SS
DQ
C6
DQ
C5
DQ
C4
DQ
C3
V
SS
V
DDQ
DQ
C2
DQ
C1
NC
V
DD
NC
V
SS
DQ
D1
DQ
D2
V
DDQ
V
SS
DQ
D3
DQ
D4
DQ
D5
DQ
D6
V
SS
V
DDQ
DQ
D7
DQ
D8
DQ
D9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
256K x 36
10
71
Top View
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CK
GW
BW
G
ADSC
ADSP
ADV
A
8
A
9
A
6
A
7
E
1
E
2
B
D
B
C
B
B
B
A
E
3
V
DD
V
SS
DQ
B9
DQ
B8
DQ
B7
V
DDQ
V
SS
DQ
B6
DQ
B5
DQ
B4
DQ
B3
V
SS
V
DDQ
DQ
B2
DQ
B1
V
SS
NC
V
DD
ZZ
DQ
A1
DQ
A2
V
DDQ
V
SS
DQ
A3
DQ
A4
DQ
A5
DQ
A6
V
SS
V
DDQ
DQ
A7
DQ
A8
DQ
A9
LBO
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
A
17
A
10
A
11
A
12
A
13
A
14
A
15
3/22
Rev: 1.06 9/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
A
16
© 2000, Giga Semiconductor, Inc.
Preliminary
GS880F18/36T-11/11.5/12/14/18
TQFP Pin Description
Pin Location
37, 36
35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
80
63, 62, 59, 58, 57, 56, 53, 52
68, 69, 72, 73, 74, 75, 78, 79
13, 12, 9, 8, 7, 6, 3, 2
18, 19, 22, 23, 24, 25, 28, 29
51, 80, 1, 30
58, 59, 62, 63, 68, 69, 72, 73, 74
8, 9, 12, 13, 18, 19, 22, 23, 24
51, 52, 53, 56, 57
75, 78, 79,
1, 2, 3, 6, 7
25, 28, 29, 30
87
93, 94
95, 96
95, 96
89
88
98, 92
97
86
83
84, 85
64
31
15, 41, 65, 91
5,10,17, 21, 26, 40, 55, 60, 67, 71, 76, 90
4, 11, 20, 27, 54, 61, 70, 77
14, 16, 38, 39, 42, 66
Symbol
A
0
, A
1
A
2
–A
17
A
18
DQ
A1
–DQ
A8
DQ
B1
–DQ
B8
DQ
C1
–DQ
C8
DQ
D1
–DQ
D8
DQ
A9
, DQ
B9
,
DQ
C9
, DQ
D9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
NC
BW
B
A
, B
B
B
C
, B
D
NC
CK
GW
E
1
, E
3
E
2
G
ADV
ADSP, ADSC
ZZ
LBO
V
DD
V
SS
V
DDQ
NC
Typ
e
I
I
I
I/O
Description
Address field LSBs and Address Counter preset Inputs
Address Inputs
Address Inputs
Data Input and Output pins (x36 Version)
I/O
I/O
Data Input and Output pins
Data Input and Output pins
—
I
I
I
—
I
I
I
I
I
I
I
I
I
I
I
I
—
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQ
A
, DQ
B
Data I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
Data I/Os; active low (x36 Version)
No Connect (x18 Version)
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active high
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep mode control; active high
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
No Connect.
Rev: 1.06 9/2000
4/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary
GS880F18/36T-11/11.5/12/14/18
GS880F18/36 Block Diagram
Register
A0–An
D
Q
A0
D0
A1
D1
Q1
Counter
Load
A
Q0
A0
A1
LBO
ADV
CK
ADSC
ADSP
GW
BW
B
A
Register
Memory
Array
Q
D
Q
D
Register
36
4
36
D
B
B
Q
Register
D
B
C
Q
Q
Register
D
Register
Q
Register
D
D
B
D
Q
Register
D
Q
E
1
E
2
E
3
Register
D
Q
Register
D
Q
0
G
Power Down
Control
1
ZZ
DQx0–DQx9
Note: Only x36 version shown for simplicity.
Rev: 1.06 9/2000
5/22
© 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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