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IDT709189L12PF9

Description
Dual-Port SRAM, 64KX9, 12ns, CMOS, PQFP100, TQFP-100
Categorystorage    storage   
File Size178KB,15 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT709189L12PF9 Overview

Dual-Port SRAM, 64KX9, 12ns, CMOS, PQFP100, TQFP-100

IDT709189L12PF9 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time12 ns
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density589824 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX9
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
HIGH-SPEED 64K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
Features
x
x
IDT709189L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 7.5/9/12ns (max.)
Low-power operation
– IDT709189L
Active: 1.2W (typ.)
Standby: 2.5mW (typ.)
Flow-Through or Pipelined output mode on either Port via
the
FT/PIPE
pins
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
Full synchronous operation on both ports
– 4ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 7.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 12ns cycle time, 83MHz operation in Pipelined output mode
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/W
L
OE
L
CE
0L
CE
1L
R/W
R
OE
R
CE
0R
CE
1R
1
0
0/1
1
0
0/1
FT/PIPE
L
0/1
1
0
0
1
0/1
FT/PIPE
R
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
I/O
Control
I/O
Control
A
15L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
15R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
4848 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc.
DSC-4848/3
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