IDT709189L9PFI datasheet, PDF - EEWORLD Datasheet

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IDT709189L9PFI: DescriptionDual-Port SRAM, 64KX9, 20ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size175KB，15 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT709189L9PFI Overview

Dual-Port SRAM, 64KX9, 20ns, CMOS, PQFP100, TQFP-100

IDT709189L9PFI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFP
package instruction	TQFP-100
Contacts	100
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.B
Maximum access time	20 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
memory density	589824 bit
Memory IC Type	DUAL-PORT SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64KX9
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm

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HIGH-SPEED 64K x 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

Features

IDT709189L

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial: 7.5/9/12ns (max.)

Low-power operation

– IDT709189L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

Flow-Through or Pipelined output mode on either Port via

the

FT/PIPE

pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 12ns cycle time, 83MHz operation in Pipelined output mode

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Functional Block Diagram

R/W

0/1

FT/PIPE

0/1

FT/PIPE

I/O

- I/O

I/O

- I/O

I/O

Control

I/O

Control

15L

CLK

ADS

CNTEN

CNTRST

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

15R

CLK

ADS

CNTEN

CNTRST

4848 drw 01

JANUARY 2001

DSC-4848/3

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