PC87200 PCI to ISA Bridge
June
2004
Revision 1.4
PC87200 PCI to ISA Bridge
1.0 General Description
The PC87200 Enhanced Integrated PCI-to-ISA bridge
works with an LPC chipset to provide ISA slot support. It is
a complement to the National Semiconductor PC8736x
Super I/O family.
2.2 PCI-to-ISA Bridge
– PCI 2.1 compliant 33 MHz bus
– Supports PCI initiator-to-ISA and ISA master-to-PCI
cycle translations
– Subtractive agent for unclaimed transactions (see the
PROHIBIT signal description for exceptions)
– Parallel to Serial IRQ conversion including
IRQ3,4,5,6,7,9,10,11,12,14,15
– Supports 4 ISA slots directly without buffering
– Programmable ISA clock (8.33 to 11 MHz)
– Slow slew rate on edges
2.0 Features
2.1 General
– Functionally compatible with Intel 82380AB
– 5.0 V tolerant PCI and ISA interfaces
– Slave mode serialized IRQ support for both quiet and
continuous modes
– PC/PCI DMA support
– 32-bit address decode for the 1MB BIOS ROM
– Supports ISA bus mastering
– 160-pin PQFP package
2.3 "PROHIBIT" functional support
– Disables PCI bus subtractive decoding when PRO-
HIBIT is asserted
Block Diagram
PCI Bus
Serialized IRQ
Interface
PCI to X-Bus / X-Bus to PCI Bridge
PC87200 Support
PCI Configuration
Registers
Decoding logic
X-Bus Arbiter
PROHIBIT
BPD#
X-Bus
PCPCIREQ#
Serial IRQ Slave
mode interface logic
ISA bus Target
Interface
ISA bus Master
Interface
PC/PCI DMA
Interface
PCPCIGNT#
ISA Bus
2004 National Semiconductor Corporation
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Table of Contents
1.0
2.0
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2
PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.3
"PROHIBIT" functional support . . . . . . . . . . . . . . . 1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1
PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2
ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.3
Serialized IRQ support . . . . . . . . . . . . . . . . . . . . . . 3
3.4
PROHIBIT signal support . . . . . . . . . . . . . . . . . . . 5
3.5
PC/PCI DMA Interface Support . . . . . . . . . . . . . . . 5
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 9
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
Chipset Register Space . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 22
8.1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . 22
8.2
PC87200Test Modes . . . . . . . . . . . . . . . . . . . . . . 22
8.3
Electrical Connections . . . . . . . . . . . . . . . . . . . . . 29
8.4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 29
8.5
Recommended Operating Conditions . . . . . . . . . 29
8.6
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 30
8.7
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.0
4.0
5.0
6.0
7.0
8.0
9.0
Revision History
Date
June 2004
Description
Rev 1.4. Correct
minor typographic errors.
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2
3.0 Device Overview
The PC87200 can be described as providing the functional ter devices, and a PC/PCI DMA master for DMA transfer
cycles. The PC87200 supports positive decode for the
blocks shown in Figure 1.
BIOS ROM in the special test mode and implements sub-
— PCI bus master/slave interface
tractive decode for unclaimed PCI accesses when the
— ISA bus master/slave interface
PROHIBIT signal is low. The PC87200 also generates
address and data parity and performs parity checking.
— Serial IRQ slave mode interface
— PROHIBIT signal support
Configuration registers are accessed through the PCI inter-
face using the PCI Bus Type 1 configuration mechanism as
— PC/PCI DMA interface
described in the PCI 2.1 Specification.
3.1 PCI Bus Interface
The PC87200 provides a PCI bus interface that is both a
slave for PCI cycles initiated by the CPU or other PCI mas-
PCI Bus
Serialized IRQ
Interface
PCI to X-Bus / X-Bus to PCI Bridge
PC87200 Support
PCI Configuration
Registers
Decoding logic
X-Bus Arbiter
PROHIBIT
BPD#
X-Bus
PCPCIREQ#
Serial IRQ Slave
mode interface logic
ISA bus Target
Interface
ISA bus Master
Interface
PC/PCI DMA
Interface
PCPCIGNT#
ISA Bus
Internal Block Diagram
3.2 ISA Bus Interface
ized IRQ defined in the Serialized IRQ on the “PCI way” -
Version 6.0 specification. Programming of the serial inter-
The PC87200 provides an ISA bus interface for subtrac-
rupt controller when the controller is currently running can
tive-decoded memory and I/O cycles on PCI. The
produce unexpected results.
PC87200 is the default subtractive decoding agent and will
forward all unclaimed memory and I/O cycles to the ISA
interface; however, the PC87200 may be configured to
ignore either I/O, memory or all unclaimed cycles (subtrac-
tive decode disabled) by asserting the PROHIBIT signal.
ISA master cycles will only be passed to the PCI bus if they
access memory. I/O accesses are left to complete on the
ISA bus.
ISA master cycles that access memory on ISA bus are not
supported by the PC87200.
3.3 Serialized IRQ support
The PC87200’s Serial Interrupt interface uses a serial
interrupt bus to transmit ISA Bus legacy interrupt requests.
The bus is a one pin bus (SERIRQ) and uses the PCI clock
as its timing reference. The serial interrupt bus is a multi-
drop bus that is shared by all PCI devices that have legacy
interrupts. The serial interrupt logic conforms to the serial-
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3.0 Device Overview
(Continued)
Timing of the serialized IRQ is illustrated as follows.
START CYCLE
START
PCI CLK
SERIRQ
Driving
Source
Slave (Q)
Master (C)
START
Master
NONE
NONE
IRQ1 Source
R
T
S
IRQ0
R
T
S
IRQ1
R
R = Recovery; T= Turn-around; S = Sample
Start Cycle Timing
IRQ15
S
PCI CLK
SERIRQ
Driving
Source
IRQ15 Source
NONE
R
T
S
IOCHK#
R
T
STOP CYCLE
STOP
(NOTE 1)
R
T
START
NONE
Master
NONE
R = Recovery; T= Turn-around; S = Sample
NOTE 1: The Stop pulse is 2 clocks wide for Quiet mode, 3 clocks wide for Continuous mode
Stop Cycle Timing
3.3.1 Serial Interrupts (Slave Mode)
There are two types of Serial Interrupt transfer modes; the
following describes the operation of the PC87200’s Serial
Interrupt Interface as a Slave:
1. Quiet Mode: Any Serial Interrupt device may initiate a
Start Cycle, while the Serial Interrupt interface is Idle, by
driving SERIRQ low for one PCI clock period. After driv-
ing low for one clock the device should immediately TRI-
STATE
®
SERIRQ, without ever driving this signal high.
A Start Cycle may not be initiated in the middle of an ac-
tive Serial Interrupt transfer. Between Stop and Start Cy-
cles the SERIRQ signal will be pulled high and the Serial
Interrupt interface will be Idle.
When the PC87200 Serial Interrupt interface must ini-
tiate a Start Cycle in order to transfer any pending inter-
rupt request to the Master. The only exception to this
requirement is when a Serial Interrupt transfer sequence
is already in progress and the PC87200 can transfer the
request during this present Serial Interrupt transfer se-
quence, then the Serial Interrupt device is not required to
generate another Start Cycle.
2. Continuous Mode: The PC87200 tracks both the Start
and Stop Frames and is responsible for inserting its in-
terrupt requests on the appropriate IRQ frames.
3.3.2 IRQ Sampling Periods
IRQ Sample Period is three clocks long, with the first clock
being the Sampled phase, the second clock being the
Recovery phase, and the third clock being the Turn-around
phase. During the Sample phase the Serial Interrupt
device drives SERIRQ low if its associated IRQ signal/data
is presently low. If its IRQ signal/data is high the Serial
Interrupt device must TRI-STATE SERIRQ. During the
Recovery phase, the Serial Interrupt device that drove
SERIRQ low (if any Serial Interface device does) is
required to drive back high. During the Turn-around phase
all Serial Interface devices will TRI-STATE SERIRQ. All
Serial Interface devices will drive SERIRQ low at the
appropriate sample point regardless of which device initi-
ated the sample activity, if its associated IRQ signal/data is
low.
Slave
The PC87200 will support the interrupt request frames
listed in the following table.
The Generation clock for each IRQ follows the low to high
edge of the Start Pulse by the number of PCI Clocks listed
in Table 1.
Note: : The number of clocks equals:
(3 x (IRQ number + 1)) - 1
3.3.3 Stop Cycle Control
The PC87200 will monitor SERIRQ for a Stop Cycle, so
that it may initiate a Start Cycle for a pending transition in
Once a Start Cycle has been initiated all Serial Interrupt any of its IRQs (Quiet Mode). For Continuous Mode, the
devices watch for the rising edge of the Start Pulse and PC87200 will not initiate any Start Cycle, but will track the
start counting IRQ Sample periods from that point. Each Start and Stop Cycles and insert its IRQs appropriately.
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3.0 Device Overview
(Continued)
Table 1. SERIRQ Slave Generation Periods
SERIRQ
Period
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
21:18
Signal Generated
Reserved.
Reserved.
Reserved.
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Reserved.
IRQ9
IRQ10
IRQ11
IRQ12
Reserved.
IRQ14
IRQ15
IOCHK#
Reserved.
# of clocks past
Start
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
62,59,56, 53
3.4 PROHIBIT signal support
The chipset will use this signal to claim the BIOS first and
then deassert the "PROHIBIT" signal to configure the PCI
to ISA bridge to continue the boot sequence.
Special test mode support is provided by means of the
BPD# pin. When this test mode is active, the PC87200 will
enable positive memory decode during boot up to enable
the host to look for boot ROM on ISA card.
PROHIBIT will be a don’t care in this test mode at boot up
for the ROM BIOS range, but should function normally after
booting
3.5 PC/PCI DMA Interface Support
The PC87200 operates as a PC/PCI DMA Secondary Arbi-
tration Bridge. The PC87200 can pass all seven legacy ISA
bus DMA channel requests to the PC/PCI DMA Primary
Bus Arbiter using the channel passing protocol defined in
the Moble PC/PCI DMA Arbitration and Protocol Specifica-
tion (Revision 2.2). Figure 1 shows the topology of the
PC87200 PC/PCI DMA requests and grants:
The PC87200 converts the seven legacy ISA bus DMA
requests (DREQ0, 1, 2, 3, 5, 6 and 7) into a serial PC/PCI
DMA compliant REQ# sequence and converts the corre-
sponding PC/PCI DMA GNT# sequence into the appropri-
ate DMA acknowledge (DACK0-3, 5-7#). This PC/PCI DMA
expansion Channel Passing Protocol is illustrated
Figure 2.
PC/PCI DMA
Primary Bus
Arbiter
PCI Bus
PCPCIGNT#
PCPCIREQ#
PC87200
PC/PCI DMA Interface Support
DACK6#
DREQ6
DACK2#
DREQ2
DACK0#
DREQ0
DACK1#
DREQ1
DACK3#
DREQ3
DACK5#
DREQ5
DACK7#
DREQ7
ISA Bus
Figure 1. PC87200 PC/PCI DMA Topology
PCICLK
PCPCIREQ#
PCPCIGNT#
start
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
start
bit 0
bit 1
bit 2
Figure 2. Channel Passing Protocol
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