EEWORLDEEWORLDEEWORLD

Part Number

Search

ISPLSI2128A-80LQN160

Description
EE PLD, 18.5ns, 128-Cell, CMOS, PQFP160, LEAD FREE, PLASTIC, QFP-160
CategoryProgrammable logic devices    Programmable logic   
File Size337KB,13 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Environmental Compliance  
Download Datasheet Parametric Compare View All

ISPLSI2128A-80LQN160 Overview

EE PLD, 18.5ns, 128-Cell, CMOS, PQFP160, LEAD FREE, PLASTIC, QFP-160

ISPLSI2128A-80LQN160 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerLattice
Parts packaging codeQFP
package instructionQFP, QFP160,1.2SQ
Contacts160
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresYES
maximum clock frequency57 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G160
JESD-609 codee3
JTAG BSTNO
length28 mm
Humidity sensitivity level3
Dedicated input times4
Number of I/O lines128
Number of macro cells128
Number of terminals160
Maximum operating temperature70 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 128 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP160,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)245
power supply5 V
Programmable logic typeEE PLD
propagation delay18.5 ns
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width28 mm
Lead-
Free
Package
Options
Available!
ispLSI 2128/A
In-System Programmable High Density PLD
Functional Block Diagram
Output Routing Pool (ORP)
D7
D6
D5
D4
Output Routing Pool (ORP)
D3
D2
D1
D0
C7
®
Features
• ENHANCEMENTS
— ispLSI 2128A is Fully Form and Function Compatible
to the ispLSI 2128, with Identical Timing
Specifcations and Packaging
— ispLSI 2128A is Built on an Advanced 0.35 Micron
E
2
CMOS
®
Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
6000 PLD Gates
128 I/O Pins, Eight Dedicated Inputs
128 Registers
High Speed Global Interconnect
Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
Output Routing Pool (ORP)
A0
Output Routing Pool (ORP)
S
C6
D
Q
Select devices have been discontinued.
See Ordering Information section for product status.
A1
A2
ES
IG
D
Q
A3
Output Routing Pool (ORP)
A4
D
Q
GLB
C3
A5
C2
D
D
Q
A6
C1
EW
A7
Global Routing Pool (GRP)
B2
B3
B4
B5
B6
B7
C0
f
max
= 100 MHz Maximum Operating Frequency
t
pd
= 10 ns Propagation Delay
TTL Compatible Inputs and Outputs
Electrically Erasable and Reprogrammable
Non-Volatile
100% Tested at Time of Manufacture
Unused Product Term Shutdown Saves Power
Output Routing Pool (ORP)
Output Routing Pool (ORP)
N
CLK 0
CLK 1
CLK 2
0139(9A)/2128
B0
B1
• IN-SYSTEM PROGRAMMABLE
U
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
SE
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
SI
21
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
28
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
E
is
pL
FO
R
Description
The ispLSI 2128 and 2128A are High Density Program-
mable Logic Devices. The devices contains128 Registers,
128 Universal I/O pins, eight Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The ispLSI 2128 and 2128A feature 5V in-
system programmability and in-system diagnostic
capabilities. The ispLSI 2128 and 2128A offer non-
volatile reprogrammability of the logic, as well as the
interconnect to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1 .. D7
(Figure 1). There are a total of 32 GLBs in the ispLSI 2128
and 2128A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
August 2006
2128_10
1
Output Routing Pool (ORP)
Logic
Array
N
C5
C4

ISPLSI2128A-80LQN160 Related Products

ISPLSI2128A-80LQN160 ISPLSI2128A-80LT176 ISPLSI2128A-100LQN160 ISPLSI2128A-80LTN176 ISPLSI2128A-100LT176 ISPLSI2128A-80LT176I ISPLSI2128A-80LQ160 ISPLSI2128A-100LQ160 ISPLSI2128A-80LTN176I ISPLSI2128A-100LTN176
Description EE PLD, 18.5ns, 128-Cell, CMOS, PQFP160, LEAD FREE, PLASTIC, QFP-160 EE PLD, 18.5ns, 128-Cell, CMOS, PQFP176, TQFP-176 EE PLD, 13ns, 128-Cell, CMOS, PQFP160, LEAD FREE, PLASTIC, QFP-160 EE PLD, 18.5ns, 128-Cell, CMOS, PQFP176, LEAD FREE, TQFP-176 EE PLD, 13ns, 128-Cell, CMOS, PQFP176, TQFP-176 EE PLD, 18.5ns, 128-Cell, CMOS, PQFP176, TQFP-176 EE PLD, 18.5ns, 128-Cell, CMOS, PQFP160, PLASTIC, QFP-160 EE PLD, 13ns, 128-Cell, CMOS, PQFP160, PLASTIC, QFP-160 EE PLD, 18.5ns, 128-Cell, CMOS, PQFP176, LEAD FREE, TQFP-176 EE PLD, 13ns, 128-Cell, CMOS, PQFP176, LEAD FREE, TQFP-176
Is it lead-free? Lead free Contains lead Lead free Lead free Contains lead Contains lead Contains lead Contains lead Lead free Lead free
Is it Rohs certified? conform to incompatible conform to conform to incompatible incompatible incompatible incompatible conform to conform to
Parts packaging code QFP QFP QFP QFP QFP QFP QFP QFP QFP QFP
package instruction QFP, QFP160,1.2SQ TQFP-176 QFP, QFP160,1.2SQ LFQFP, QFP176,1.0SQ,20 TQFP-176 TQFP-176 PLASTIC, QFP-160 PLASTIC, QFP-160 LFQFP, QFP176,1.0SQ,20 LFQFP, QFP176,1.0SQ,20
Contacts 160 176 160 176 176 176 160 160 176 176
Reach Compliance Code compliant not_compliant compliant compliant not_compliant not_compliant compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
Other features YES YES YES YES YES YES YES YES YES YES
maximum clock frequency 57 MHz 57 MHz 77 MHz 57 MHz 77 MHz 57 MHz 57 MHz 77 MHz 57 MHz 77 MHz
In-system programmable YES YES YES YES YES YES YES YES YES YES
JESD-30 code S-PQFP-G160 S-PQFP-G176 S-PQFP-G160 S-PQFP-G176 S-PQFP-G176 S-PQFP-G176 S-PQFP-G160 S-PQFP-G160 S-PQFP-G176 S-PQFP-G176
JESD-609 code e3 e0 e3 e3 e0 e0 e0 e0 e3 e3
JTAG BST NO NO NO NO NO NO NO NO NO NO
length 28 mm 24 mm 28 mm 24 mm 24 mm 24 mm 28 mm 28 mm 24 mm 24 mm
Humidity sensitivity level 3 3 3 3 3 3 3 3 3 3
Dedicated input times 4 4 4 4 4 4 4 4 4 4
Number of I/O lines 128 128 128 128 128 128 128 128 128 128
Number of macro cells 128 128 128 128 128 128 128 128 128 128
Number of terminals 160 176 160 176 176 176 160 160 176 176
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 85 °C 70 °C 70 °C 85 °C 70 °C
organize 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O 4 DEDICATED INPUTS, 128 I/O
Output function MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL MACROCELL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code QFP LFQFP QFP LFQFP LFQFP LFQFP QFP QFP LFQFP LFQFP
Encapsulate equivalent code QFP160,1.2SQ QFP176,1.0SQ,20 QFP160,1.2SQ QFP176,1.0SQ,20 QFP176,1.0SQ,20 QFP176,1.0SQ,20 QFP160,1.2SQ QFP160,1.2SQ QFP176,1.0SQ,20 QFP176,1.0SQ,20
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form FLATPACK FLATPACK, LOW PROFILE, FINE PITCH FLATPACK FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH FLATPACK FLATPACK FLATPACK, LOW PROFILE, FINE PITCH FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius) 245 225 245 225 225 225 225 225 260 260
power supply 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Programmable logic type EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD EE PLD
propagation delay 18.5 ns 18.5 ns 13 ns 18.5 ns 13 ns 18.5 ns 18.5 ns 13 ns 18.5 ns 13 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.1 mm 1.6 mm 4.1 mm 1.6 mm 1.6 mm 1.6 mm 4.1 mm 4.1 mm 1.6 mm 1.6 mm
Maximum supply voltage 5.25 V 5.25 V 5.25 V 5.25 V 5.25 V 5.5 V 5.25 V 5.25 V 5.5 V 5.25 V
Minimum supply voltage 4.75 V 4.75 V 4.75 V 4.75 V 4.75 V 4.5 V 4.75 V 4.75 V 4.5 V 4.75 V
Nominal supply voltage 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES YES YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL INDUSTRIAL COMMERCIAL
Terminal surface Matte Tin (Sn) Tin/Lead (Sn85Pb15) Matte Tin (Sn) Matte Tin (Sn) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Matte Tin (Sn) Matte Tin (Sn)
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.5 mm 0.65 mm 0.5 mm 0.5 mm 0.5 mm 0.65 mm 0.65 mm 0.5 mm 0.5 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature 40 30 40 NOT SPECIFIED 30 30 30 30 40 40
width 28 mm 24 mm 28 mm 24 mm 24 mm 24 mm 28 mm 28 mm 24 mm 24 mm
Maker Lattice - - - Lattice Lattice Lattice Lattice Lattice Lattice
Experience that e-sports players should have
ICECUT After 2 years, I finally want to write something for the 2009 students. Because you will have 72 hours to complete this competition in September this year. Success means a lot to you. 1. Many p...
小瑞 Electronics Design Contest
Getting Started with STM32 in One Day
To master STM32, you only need the following three tools: "STM32 Chinese Reference Manual" and "CM3 Authoritative Guide CnR2" firmware library. Why do you only need these three official documents? Ple...
slytton stm32/stm8
Q&A: AMP03 internal op amp gain question
AMP03 is a unit-gain differential amplifier, so what is the internal amplifier gain? I just want to know the amplifier in the film. Official information: [url]http://www.analog.com/zh/specialty-amplif...
sacq ADI Reference Circuit
There are many options for selecting external crystal oscillators for the MSP430 G2 series.
[i=s]This post was last edited by helloxieyu on 2014-8-15 15:26[/i] There are multiple options for external crystal oscillators for the MSP430 G2 series. 1. In addition to 32.768K passive crystals, ca...
helloxieyu Microcontroller MCU
Why doesn't my ccs5 have auto-completion?
As the title says. I have turned on the detection of operators like :: in the settings, but it cannot automatically complete the operation when operating registers. I have included the correct header ...
xxxxfghjxxxx Microcontroller MCU
[NUCLEO-WL55JC2 Evaluation 3] Building the NUCLEO-WL55JC2 MDK development and testing environment
[i=s]This post was last edited by nich20xx on 2020-7-3 22:50[/i] # 1 Introduction After having a systematic understanding of NUCLEO-WL55JC2, I started running the sample code of NUCLEO-WL55JC2. Since ...
nich20xx Special Edition for Assessment Centres

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1733  211  897  2619  2822  35  5  19  53  57 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号