ISPLSI2032A-180LJN44 datasheet, PDF

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ISPLSI2032A-180LJN44: DescriptionEE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44; CategoryProgrammable logic devices Programmable logic; File Size397KB，16 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com; Environmental Compliance

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ISPLSI2032A-180LJN44 Overview

EE PLD, 7.5ns, 32-Cell, CMOS, PQCC44, LEAD FREE, PLASTIC, LCC-44

ISPLSI2032A-180LJN44 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Lattice
Parts packaging code	LCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	compliant
ECCN code	EAR99
Other features	YES
maximum clock frequency	125 MHz
In-system programmable	YES
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
JTAG BST	NO
length	16.5862 mm
Humidity sensitivity level	3
Dedicated input times
Number of I/O lines	32
Number of macro cells	32
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 32 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
power supply	5 V
Programmable logic type	EE PLD
propagation delay	7.5 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.5862 mm

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Lead-

Free

Package

Options

Available!

ispLSI 2032/A

In-System Programmable High Density PLD

Functional Block Diagram

Features

• ENHANCEMENTS

— ispLSI 2032A is Fully Form and Function Compatible

to the ispLSI 2032, with Identical Timing

Specifcations and Packaging

— ispLSI 2032A is Built on an Advanced 0.35 Micron

CMOS

Technology

• HIGH DENSITY PROGRAMMABLE LOGIC

Output Routing Pool (ORP)

Select devices have been discontinued.

See Ordering Information section for product status.

Output Routing Pool (ORP)

—

1000 PLD Gates

32 I/O Pins, Two Dedicated Inputs

32 Registers

High Speed Global Interconnect

Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

Input Bus

GLB

Logic

Array

D Q

max

= 180 MHz Maximum Operating Frequency

= 5.0 ns Propagation Delay

TTL Compatible Inputs and Outputs

Electrically Erasable and Reprogrammable

Non-Volatile

100% Tested at Time of Manufacture

Unused Product Term Shutdown Saves Power

0139Bisp/2000

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

— Lead-Free Package Options

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

Market and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

to change without notice.

The ispLSI 2032 and 2032A are High Density Program-

mable Logic Devices. The devices contain 32 Registers,

32 Universal I/O pins, two Dedicated Input Pins, three

Dedicated Clock Input Pins, one dedicated Global OE

input pin and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The ispLSI 2032 and 2032A feature 5V in-

system programmability and in-system diagnostic

capabilities. The ispLSI 2032 and 2032A offer non-

volatile reprogrammability of the logic, as well as the

interconnect to provide truly reconfigurable systems.

The basic unit of logic on these devices is the Generic

Logic Block (GLB). The GLBs are labeled A0, A1 .. A7

(Figure 1). There are a total of eight GLBs in the ispLSI

2032 and 2032A devices. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

Description

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

August 2006

2032_11

Input Bus

D Q

Global Routing Pool

(GRP)

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