M48T37Y
M48T37V
3.3V-5V 256 Kbit (32Kb x8) TIMEKEEPER
®
SRAM
s
INTEGRATED ULTRA-LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK SOFTWARE CALIBRATION
YEAR 2000 COMPLIANT
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WATCHDOG TIMER
WRITE PROTECT VOLTAGE
(V
PFD
= Power-Fail Deselect Voltage):
– M48T37Y: 4.2V
≤
V
PFD
≤
4.5V
– M48T37V: 2.7V
≤
V
PFD
≤
3.0V
44
SNAPHAT (SH)
Battery
s
s
s
s
s
1
SOH44 (MH)
s
PACKAGING INCLUDES a 44-LEAD SOIC and
SNAPHAT TOP (to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT
®
TOP which
CONTAINS the BATTERY and CRYSTAL
MICROPROCESSOR POWER-ON RESET
(Valid even during battery back-up mode)
PROGRAMMABLE ALARM OUTPUT ACTIVE
in the BATTERY BACKED-UP
BATTERY LOW FLAG
A0-A14
15
VCC
8
DQ0-DQ7
RST
IRQ/FT
s
Figure 1. Logic Diagram
s
s
s
Table 1. Signal Names
A0-A14
DQ0-DQ7
RST
IRQ/FT
WDI
E
G
W
V
CC
V
SS
NC
February 2000
Address Inputs
Data Inputs / Outputs
Power Fail Reset Output (Open Drain)
Interrupt / Frequency Test Output
(Open Drain)
Watchdog Input
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
Not connected Internally
1/20
W
E
G
WDI
M48T37Y
M48T37V
VSS
AI02172
M48T37Y, M48T37V
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
Parameter
Grade 1
Ambient Operating Temperature
Grade 6
SNAPHAT
T
STG
T
SLD (2)
V
IO
Storage Temperature (V
CC
Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
M48T37Y
Input or Output Voltages
M48T37V
M48T37Y
V
CC
I
O
P
D
Supply Voltage
M48T37V
Output Current
Power Dissipation
–0.3 to 4.6
10
1
V
mA
W
–0.3 to 4.6
–0.3 to 7
V
V
SOIC
–40 to 85
–40 to 85
–55 to 125
260
–0.3 to 7
Value
0 to 70
Unit
°C
°C
°C
°C
°C
V
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION:
Do NOT wave solder SOIC to avoid damaging SNAPH AT sockets.
Figure 2. SOIC Connections
NC
RST
NC
NC
A14
A12
A7
A6
A5
A4
A3
NC
NC
WDI
A2
A1
A0
DQ0
DQ1
DQ2
NC
VSS
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
35
10
11 M48T37Y 34
12 M48T37V 33
13
32
14
31
15
30
29
16
17
28
18
27
19
26
20
25
21
24
22
23
AI02174
VCC
NC
NC
NC
IRQ/FT
W
A13
A8
A9
A11
G
NC
NC
A10
E
NC
DQ7
DQ6
DQ5
DQ4
DQ3
NC
DESCRIPTION
The M48T37Y/37V TIMEKEEPER® RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in a special
package which provides a highly integrated bat-
tery backed-up memory and real time clock solu-
tion.
The 44 lead 330mil SOIC package provides sock-
ets with gold-plated contacts at both ends for di-
rect connection to a separate SNAPHAT housing
containing the battery and crystal. The unique de-
sign allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape &Reel
form. For the 44 lead SOIC, the battery/crystal
package (i.e. SNAPHAT) part number is ”M4T28-
BR12SH” or ”M4T32-BR12SH”.
Caution:
Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T37Y/37V are integrated on one silicon chip.
2/20
M48T37Y, M48T37V
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
5ns
0 to 3V
1.5V
DEVICE
UNDER
TEST
645Ω
Figure 4. AC Testing Load Circuit
Note that Output Hi-Z is defined as the point where data is no longer
driven.
The memory locations, to provide user accessible
BYTEWIDE™ clock information are in the bytes
with addresses 7FF1 and 7FF9h-7FFFh (located
in Table 11). The clock locations contain the cen-
tury, year, month, date, day, hour, minute, and
second in 24 hour BCD format. Corrections for 28,
29 (leap year-compliant until the year 2100), 30,
and 31 day months are made automatically.
Byte 7FF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
Byte 7FF7h contains the watchdog timer setting.
The watchdog timer redirects an out-of-control mi-
croprocessor and provides a reset or interrupt to it.
Byte 7FF2h-7FF5h are reserved for clock alarm
programming.
These bytes can be used to set the alarm. This will
generate an active low signal on the IRQ/FT pin
when the alarm bytes match the date, hours, min-
utes and seconds of the clock. The eight clock
bytes are not the actual clock counters them-
selves; they are memory locations consisting of Bi-
PORT™ read/write memory cells. The M48T37Y/
37V includes a clock control circuit which updates
the clock bytes with current information once per
second. The information can be accessed by the
user in the same manner as any other location in
the static memory array.
The M48T37Y/37V also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single V
CC
supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
writes protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below the Battery Back-up Switchover Voltage
(V
SO
), the control circuitry connects the battery
which maintains data and clock operation until val-
id power returns.
CL = 100pF
1.75V
CL includes JIG capacitance
AI02325
Note: Excluding open-drain output pins.
READ MODE
The M48T37Y/37V is in the Read Mode whenever
Write Enable (W) is high and Chip Enable (E) is
low. The unique address specified by the 15 Ad-
dress Inputs defines which one of the 32,752 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
AVQV
) after the last address input signal is
stable, providing that the E and Output Enable (G)
access times are also satisfied. If the E and G ac-
cess times are not met, valid data will be available
after the latter of the Chip Enable Access time
(t
ELQV
) or Output Enable Access time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
.
If the Address Inputs are changed while E and G
remain active, output data will remain valid for Out-
put Data Hold time (t
AXQX
) but will be indetermi-
nate until the next Address Access.
4/20
FPGA/CPLD
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