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HY27UG084GDM-TIS

Description
Flash, 512MX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48
Categorystorage    storage   
File Size438KB,53 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Download Datasheet Parametric View All

HY27UG084GDM-TIS Overview

Flash, 512MX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, TSOP1-48

HY27UG084GDM-TIS Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSK Hynix
Parts packaging codeTSOP1
package instructionTSOP1,
Contacts48
Reach Compliance Codeunknown
ECCN code3A991.B.1.A
Maximum access time30 ns
JESD-30 codeR-PDSO-G48
length18.4 mm
memory density4294967296 bit
Memory IC TypeFLASH
memory width8
Number of functions1
Number of terminals48
word count536870912 words
character code512000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Programming voltage3.3 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
typeSLC NAND TYPE
width12 mm
Preliminary
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Document Title
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Add Errata
tWH
tWP
25
35
tWC
50
60
History
Draft Date
May. 13. 2005
Remark
Preliminary
0.1
Specification
Relaxed value
15
20
May. 23. 2005
Preliminary
1) Correct the Valid Blocks Number.
0.2
Valid Blocks (max)
Before
After
4,098
4,096
Jun. 13. 2005
Preliminary
1) Add tRSBY (Table 11)
- tRSBY (Dummy Busy Time for Cache Read)
0.3
- tRSBY is 5us (typ.)
2) Edit Figure 18, 19
3) Correct Extended Read Status Register Commands (Table. 19)
1) Add ULGA Package.
- Figures & texts are added.
2) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
Before
VIN=VOUT=0 to 3.6V
VIN=VOUT=0 to Vcc (max)
JUn. 14. 2005
Preliminary
0.4
After
Sep. 02. 2005
Preliminary
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
Rev 0.5 / Oct. 2005
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