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X4045M8IZ

Description
CPU Supervisor with 4kbit EEPROM; MSOP8, PDIP8, SOIC8; Temp Range: See Datasheet
CategoryPower/power management    The power supply circuit   
File Size889KB,24 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Environmental Compliance
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X4045M8IZ Overview

CPU Supervisor with 4kbit EEPROM; MSOP8, PDIP8, SOIC8; Temp Range: See Datasheet

DATASHEET
X4043, X4045
4k, 512 x 8 Bit CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
—Five standard reset threshold voltages
—Adjust low V
CC
reset threshold voltage using
special programming sequence
—Reset signal valid to V
CC
= 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lock
protection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
falls below the minimum V
CC
trip
point. RESET/RESET is asserted until V
CC
returns to
proper operating level and stabilizes. Five industry stan-
dard V
TRIP
thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
FN8118
Rev 3.00
December 9, 2015
BLOCK DIAGRAM
Watchdog Transition
Detector
WP
SDA
Data
Register
Block Lock Control
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
V
CC
V
TRIP
Protect Logic
Status
Register
EEPROM Array
2Kbits 1Kb 1Kb
RESET (X4043)
RESET (X4045)
Reset &
Watchdog
Timebase
Watchdog
Timer Reset
SCL
+
-
Power-on and
Low Voltage
Reset
Generation
FN8118 Rev 3.00
December 9, 2015
Page 1 of 24
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