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8
8
Platform Flash XL High-Density Configuration
and Storage Device
Product Specification
DS617 (v4.0) August 5, 2015
Features
•
•
•
•
•
•
•
•
•
•
•
In-System Programmable Flash Memory Optimized for
Virtex®-5 or Virtex-6 FPGA Configuration
High-Performance FPGA Bitstream Transfer up to
800 Mb/s (50 MHz
×
16-bits), Ideal for
PCI Express® Endpoint Applications
MultiBoot Bitstream, Design Revision Storage
FPGA Configuration Synchronization (READY_WAIT)
Handshake Signal
ISE® Software Support for In-System Programming via
Xilinx® JTAG Cables
Standard NOR-Flash Interface for Access to Code or
Data Storage
Operation over Full Industrial Temperature Range
(–40°C to +85°C)
Common Flash Interface (CFI)
Low-Power Advanced CMOS NOR-Flash Process
Endurance of 10,000 Program/Erase Cycles Per Block
Power Supplies
♦
♦
•
Memory Organization
♦
♦
♦
♦
♦
128-Mb Main Array Capacity
16-bit Data Bus
Multiple 8-Mb Bank Architecture for Dual
Erase/Program and Read Operation
127 Regular 1-Mb Main Blocks
4 Small 256-Kb Parameter Blocks
Power-On in Synchronous Burst Read Mode
Asynchronous Random Access Mode
Accelerated Asynchronous Page Read Mode
Default Block Protection at Power-Up
Hardware Write Protection (when V
PP
= V
SS
)
Unique Device Number (64-bits)
One-Time-Programmable (OTP) Registers
•
Synchronous/Asynchronous Read Modes
♦
♦
♦
•
Protection
♦
♦
•
Security
♦
♦
Industry-Standard Core Power Supply Voltage
(V
DD
) = 1.8V
3.3V or 2.5V I/O (V
DDQ
) Power Supply Voltage
•
Small-Footprint (10 mm
×
13 mm) FT64 Packaging
Description
A reliable compact high-performance configuration
bitstream storage and delivery solution is essential for the
high-density FPGAs. Platform Flash XL is the industry's
highest performing configuration and storage device and is
specially optimized for high-performance FPGA
configuration. Platform Flash XL integrates 128 Mb of
in-system programmable flash storage and performance
features for configuration within a small-footprint FT64
package (Figure
5).
Power-on burst read mode and
dedicated I/O power supply enable Platform Flash XL to
mate seamlessly with the native SelectMAP configuration
interface. A wide, 16-bit data bus delivers the FPGA
configuration bitstream at speeds up to 800 Mb/s without
wait states. See
UG438,
Platform Flash XL Configuration
and Storage Device User Guide,
for system-level usage and
performance considerations.
Platform Flash XL is supported for use with Virtex-5 or Virtex-6
FPGAs only. Use with older Virtex families, Spartan® families,
or AES encrypted bitstreams is not supported.
Platform Flash XL is a non-volatile flash storage solution,
optimized for FPGA configuration. The device provides a
READY_WAIT signal that synchronizes the start of the FPGA
configuration process, improving both system reliability and
simplifying board design. Platform Flash XL can download an
XC5VLX330 bitstream (79,704,832 bits) in less than 100 ms,
making the configuration performance of Platform Flash XL
ideal for PCI Express endpoints and other high-performance
applications.
Platform Flash XL is a single-chip configuration solution with
additional system-level capabilities. A standard NOR flash
interface (Figure
2)
and support for common flash interface
(CFI) queries provide industry-standard access to the device
memory space. The Platform Flash XL's 128 Mb capacity can
typically hold one or more FPGA bitstreams. Any memory
space not used for bitstream storage can be used to hold
general purpose data or embedded processor code.
© Copyright 2007–2015 Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS617 (v4.0) August 5, 2015
Product Specification
www.xilinx.com
1
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Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 1
Platform Flash XL
READY_WAIT
Clock
up
to 50 MHz
(1)
FPGA Design
(.bit) File
Wide (16-bit) Datapath
Up to
800
Mb/s
SelectMAP
(x16)
Port
Configuration
Synchronization
Handshake
FPGA
DS617_01_102709
Notes:
1.
System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the
maximum configuration clock frequency, check the minimum clock period (T
KHKH
) for the chosen I/O voltage range (V
DDQ
), the clock High-
to-output valid time (T
KHQV
), and the FPGA SelectMAP setup time.
Figure 1:
Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration
Platform Flash XL support is integrated with the Xilinx
design and debug tool suite.The iMPACT application,
included with the ISE software, supports indirect, in-system
programming of Platform Flash XL via the IEEE Standard
1149.1 (JTAG) port on the FPGA for prototype programming
(Figure
3).
X-Ref Target - Figure 2
Platform Flash XL
Code
User Data
Design (.bit)
File, Rev. 1
Design (.bit)
File, Rev. 0
Control
Address
FPGA
User Design
Data/Commands
DS617_02_081209
Figure 2:
Standard NOR Flash Interface for User
Access to Memory
X-Ref Target - Figure 3
Single
Cable Connector for
Direct FPGA Configuration/Debug
and
Indirect Platform Flash XL
Programming
IEEE 1149.1
(JTAG) Port
Xilinx JTAG
Cable Connector
FPGA
For Programming
Platform Flash XL
Platform Flash XL
Standard
NOR
Flash Interface
FPGA Design
(.bit) File
Control
Address
Data/Commands
BPI Flash
Configuration Port
Indirect,
In-System
Programming
Engine
For Programming
Platform Flash XL
DS617_03_081209
Figure 3:
Indirect Programming Solution for Platform Flash XL
DS617 (v4.0) August 5, 2015
Product Specification
www.xilinx.com
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Platform Flash XL High-Density Configuration and Storage Device
Flash Memory Architecture Overview
Platform Flash XL is a 128-Mb (8 Mb
×
16) non-volatile flash
memory. The device is in-system programmable with a 1.8V
core (V
DD
) power supply. A separate I/O (V
DDQ
) power supply
enables I/O operation at 3.3V or 2.5V. An optional 9V V
PP
power supply can accelerate factory programming.
A common flash interface (CFI) provides access to device
memory (Figure
3, page 3).
Moreover, Platform Flash XL
supports multiple read modes. A 23-bit address bus
provides random read access to each 16-bit word. Four
words occupy each page for accelerated page mode reads.
The device powers-up in a synchronous burst read mode
capable of sequential read rates up to 54 MHz.
Platform Flash XL has a multiple-bank architecture. An array of
131 individually erasable blocks are divided into 16, 8-Mb
banks. Fifteen main banks contain uniform blocks of
64 Kwords, and one parameter bank contains seven main
blocks of 64 Kwords, plus four parameter blocks of 16 Kwords.
Note:
The device is electronically erasable at the block level and
programmable on a word-by-word basis.
be suspended to read data at any memory location except for
the one being programmed, and then resumed.
Program and erase commands are written to the command
interface of the memory. An internal program/erase
controller takes care of the timing necessary for program
and erase operations. The end of a program or erase
operation can be detected and any error conditions
identified in the status register. The command set required
to control the memory is consistent with JEDEC standards.
The device supports synchronous burst read and
asynchronous read from all blocks of the memory array. At
power-up, the device is configured for synchronous read. In
synchronous burst read mode, data is output on each clock
cycle at frequencies of up to 54 MHz. The synchronous
burst read operation can be suspended and resumed.
When the bus is inactive during asynchronous read
operations, the device automatically switches to an
automatic standby mode. In this condition the power
consumption is reduced to the standby value, and the
outputs are still driven.
Platform Flash XL features an instant, individual block-
locking scheme, allowing any block to be locked or unlocked
with no latency, and enabling instant code and data
protection. All blocks have three levels of protection. Blocks
can be locked and locked-down individually preventing any
accidental programming or erasure. There is an additional
hardware protection against program and erase: when V
PP
= V
PPLK
all blocks are protected against program or erase.
All blocks are locked at power-up.
The device features a separate region of 17 programmable
registers whose values can be protected against further
programming changes. Sixteen of these registers are each
128-bits in size, with the 17
th
register subdivided into two 64-
bit registers. One of the 64-bit registers contains a factory
preprogrammed, unique device number, permanently
protected against modification. The second 64-bit register is
user-programmable.
All bits within these registers (except for the permanently-
protected unique number register) are one-time-
programmable (OTP) — each bit can be programmed only
once from a one-value to a zero-value.
Two protection lock registers can be programmed to lock any
of the 17 protectable registers against further changes. One
protection lock register contains bits that determine the
protection state of the two special 64-bit registers. The bit
corresponding to the unique device number register is pre-
programmed to ensure the unique device number register is
permanently protected against modification. The second
protection lock register contains OTP bits that correspond
the protection state each of the remaining 16 registers.
Platform Flash XL is available in a 10 × 13 mm, 1.0 mm-pitch
FT64 package and supplied with all the bits erased (set to '1').
The multiple-bank architecture allows dual operations —
read operations can occur on one bank while a program or
erase operation occurs in a different bank. However, only
one bank at a time is allowed to be in program or erase
mode. Burst reads are allowed to cross bank boundaries.
Table 1
summarizes the bank architecture, and the memory
map is shown in
Figure 4, page 5.
The parameter blocks are
located at the top of the memory address space in Platform
Flash XL.
Table 1:
Bank Architecture
Number
Parameter
Bank
Bank 1
Bank 2
Bank 3
Bank Size
8 Mbits
8 Mbits
8 Mbits
8 Mbits
Parameter
Blocks
4 blocks of
16 Kwords
–
–
–
Main Blocks
7 blocks of
64 Kwords
8 blocks of
64 Kwords
8 blocks of
64 Kwords
8 blocks of
64 Kwords
Bank 14
Bank 15
Each block can be erased separately. Erase operations can
be suspended in order to perform a program or read operation
in any other block and then resumed. Program operations can
DS617 (v4.0) August 5, 2015
Product Specification
…
8 Mbits
8 Mbits
…
…
–
–
8 blocks of
64 Kwords
8 blocks of
64 Kwords
…
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3
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Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 4
Address
7FFFFFh
7FC000h
7F3FFFh
16 Kword
4 Parameter
Blocks
16 Kword
64 Kword
7 Main
Blocks
64 Kword
64 Kword
8
Main
Blocks
64 Kword
64 Kword
8
Main
Blocks
64 Kword
64 Kword
8
Main
Blocks
64 Kword
Parameter
Bank
7F0000h
7EFFFFh
7E0000h
78FFFFh
780000h
77FFFFh
770000h
Bank 1
70FFFFh
700000h
6FFFFFh
6F0000h
Bank 2
68FFFFh
680000h
67FFFFh
670000h
Bank
3
60FFFFh
600000h
07FFFFh
070000h
64 Kword
8
Main
Blocks
64 Kword
DS167_04_053008
Bank 15
00FFFFh
000000h
Figure 4:
Platform Flash XL Memory Map
(Address Lines A22 – A0)
DS617 (v4.0) August 5, 2015
Product Specification
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4
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Platform Flash XL High-Density Configuration and Storage Device
Pinout and Signal Descriptions
See
Figure 5
and
Table 2
for a logic diagram and brief overview of the signals connected to this device.
Table 2:
Signal Names
Signal Name
A22-A0
DQ15-DQ0
E
G
W
RP
WP
K
L
READY_WAIT
V
DD
V
DDQ
V
PP
V
SS
V
SSQ
NC
Notes:
1.
Typically, V
PP
is tied to the V
DDQ
supply on a board. See the V
PP
Program Supply Voltage section for alternate options.
X-Ref Target - Figure 5
V
DD
V
DDQ
V
PP
Function
Address Inputs
Data Input/Outputs,
Command Inputs
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Clock
Latch Enable
Ready/Wait
Supply Voltage
Supply Voltage for
Input/Output Buffers
Optional
(1)
Supply
Voltage for Fast
Program and Erase
Ground
Ground Input/output
Supply
Not Connected
Internally
Direction
Inputs
I/O
Input
Input
Input
Input
Input
Input
Input
I/O
–
–
L
K
RP
WP
E
G
READY_WAIT
A22–A0
W
23
16
DQ15–DQ0
Platform
Flash XL
–
V
SS
V
SSQ
DS617_05_053008
–
–
–
Figure 5:
Logic Diagram
Address Inputs (A22-A0)
The Address inputs select the words in the memory array to
access during Bus Read operations. During Bus Write
operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
deselected, the outputs are high impedance, and the power
consumption is reduced to the standby level.
Output Enable (G)
The Output Enable input controls data outputs during the
Bus Read operation of the memory. Before the start of the
first address latching sequence (FALS), the Output Enable
input must be held Low before the clock starts toggling.
Data Inputs/Outputs (DQ15-DQ0)
The Data I/O output the data stored at the selected address
during a Bus Read operation or input a command or the
data to be programmed during a Bus Write operation.
Write Enable (W)
The Write Enable input controls the Bus Write operation of
the memory’s Command Interface. The data and address
inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
Chip Enable (E)
The Chip Enable input activates the memory control logic,
input buffers, decoders and sense amplifiers. When Chip
Enable is at V
IL
and Reset is at V
IH
, the device is in active
mode. When Chip Enable is at V
IH
, the memory is
DS617 (v4.0) August 5, 2015
Product Specification
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