R
Spartan-II FPGA Family
Data Sheet
Product Specification
DS001 June 13, 2008
This document includes all four modules of the Spartan
®
-II FPGA data sheet.
Module 1:
Introduction and Ordering Information
DS001-1 (v2.8) June 13, 2008
•
•
•
•
•
•
Introduction
Features
General Overview
Product Availability
User I/O Chart
Ordering Information
Module 3:
DC and Switching Characteristics
DS001-3 (v2.8) June 13, 2008
•
DC Specifications
- Absolute Maximum Ratings
- Recommended Operating Conditions
- DC Characteristics
- Power-On Requirements
- DC Input and Output Levels
Switching Characteristics
- Pin-to-Pin Parameters
- IOB Switching Characteristics
- Clock Distribution Characteristics
- DLL Timing Parameters
- CLB Switching Characteristics
- Block RAM Switching Characteristics
- TBUF Switching Characteristics
- JTAG Switching Characteristics
•
Module 2:
Functional Description
DS001-2 (v2.8) June 13, 2008
•
Architectural Description
- Spartan-II Array
- Input/Output Block
- Configurable Logic Block
- Block RAM
- Clock Distribution: Delay-Locked Loop
- Boundary Scan
Development System
Configuration
- Configuration Timing
Design Considerations
Module 4:
Pinout Tables
DS001-4 (v2.8) June 13, 2008
•
•
Pin Definitions
Pinout Tables
•
•
•
IMPORTANT NOTE:
This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the
end. Use the PDF "Bookmarks" for easy navigation in this volume.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001 June 13, 2008
Product Specification
www.xilinx.com
1
6
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Spartan-II FPGA Family:
Introduction and Ordering
Information
0
DS001-1 (v2.8) June 13, 2008
Product Specification
•
System level features
- SelectRAM™ hierarchical memory:
·
16 bits/LUT distributed RAM
·
Configurable 4K bit block RAM
·
Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
Fully supported by powerful Xilinx
®
ISE
®
development
system
- Fully automatic mapping, placement, and routing
Introduction
The Spartan
®
-II Field-Programmable Gate Array family
gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in
Table 1.
System
performance is supported up to 200 MHz. Features include
block RAM (to 56K bits), distributed RAM (to 75,264 bits),
16 selectable I/O standards, and four DLLs. Fast,
predictable interconnect means that successive design
iterations continue to meet timing requirements.
The Spartan-II family is a superior alternative to
mask-programmed ASICs. The FPGA avoids the initial
cost, lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
•
Features
•
Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex
®
FPGA
architecture
- Unlimited reprogrammability
- Very low cost
- Cost-effective 0.18 micron process
•
•
Table 1:
Spartan-II FPGA Family Members
Logic
Cells
432
972
1,728
2,700
3,888
5,292
System Gates
(Logic and RAM)
15,000
30,000
50,000
100,000
150,000
200,000
CLB
Array
(R x C)
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
Total
CLBs
96
216
384
600
864
1,176
Maximum
Available
User I/O
(1)
86
92
176
176
260
284
Total
Distributed RAM
Bits
6,144
13,824
24,576
38,400
55,296
75,264
Total
Block RAM
Bits
16K
24K
32K
40K
48K
56K
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in
Table 2, page 4.
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other
trademarks are the property of their respective owners.
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
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Spartan-II FPGA Family: Introduction and Ordering Information
serial mode), or written into the FPGA in slave serial, slave
parallel, or Boundary Scan modes.
Spartan-II FPGAs are typically used in high-volume
applications where the versatility of a fast programmable
solution adds benefits. Spartan-II FPGAs are ideal for
shortening product development cycles while offering a
cost-effective solution for high volume production.
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and
semiconductor technology. Spartan-II devices provide
system clock rates up to 200 MHz. In addition to the
conventional benefits of high-volume programmable logic
solutions, Spartan-II FPGAs also offer on-chip synchronous
single-port and dual-port RAM (block and distributed form),
DLL clock drivers, programmable set and reset on all
flip-flops, fast carry logic, and many other features.
General Overview
The Spartan-II family of FPGAs have a regular, flexible,
programmable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see
Figure 1).
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited
reprogramming cycles are possible with this approach.
Stored values in these cells determine logic functions and
interconnections implemented in the FPGA. Configuration
data can be read from an external serial PROM (master
DLL
DLL
BLOCK RAM
CLBs
CLBs
BLOCK RAM
CLBs
CLBs
DLL
I/O LOGIC
XC2S15
BLOCK RAM
DLL
DS001_01_091800
Figure 1:
Basic Spartan-II Family FPGA Block Diagram
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
BLOCK RAM
Module 1 of 4
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Spartan-II FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2
shows the maximum user I/Os available on the device and the number of user I/Os available for each
device/package combination. The four global clock pins are usable as additional user I/Os when not used as a global clock
pin. These pins are not included in user I/O counts.
Table 2:
Spartan-II FPGA User I/O Chart
(1)
Available User I/O According to Package Type
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Maximum
User I/O
86
92
176
176
260
284
VQ100
VQG100
60
60
-
-
-
-
TQ144
TQG144
86
92
92
92
-
-
CS144
CSG144
(Note 2)
92
-
-
-
-
PQ208
PQG208
-
(Note 2)
140
140
140
140
FG256
FGG256
-
-
176
176
176
176
FG456
FGG456
-
-
-
(Note 2)
260
284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
2. Discontinued by
PDN2004-01.
DS001-1 (v2.8) June 13, 2008
Product Specification
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Module 1 of 4
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Spartan-II FPGA Family: Introduction and Ordering Information
Ordering Information
Spartan-II devices are available in both standard and Pb-free packaging options for all device/package combinations. The
Pb-free packages include a special "G" character in the ordering code.
Standard Packaging
Example: XC2S50 -6 PQ 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
DS077-1_01a_072204
Pb-Free Packaging
Example: XC2S50 -6 PQ G 208 C
Device Type
Speed Grade
Package Type
Temperature Range
Number of Pins
Pb-free
DS077-1_01b_072204
Device Ordering Options
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Speed Grade
-5 Standard Performance
-6 Higher Performance
(1)
Number of Pins / Package Type
VQ(G)100
CS(G)144
TQ(G)144
PQ(G)208
FG(G)256
FG(G)456
100-pin Plastic Very Thin QFP
144-ball Chip-Scale BGA
144-pin Plastic Thin QFP
208-pin Plastic QFP
256-ball Fine Pitch BGA
456-ball Fine Pitch BGA
Temperature Range (T
J
)
C = Commercial
I = Industrial
0°C to +85°C
–40°C to +100°C
Notes:
1. The -6 speed grade is exclusively available in the Commercial temperature range.
Device Part Marking
R
Device Type
Package
Speed
Operating Range
SPARTAN
XC2S50
TM
PQ208AFP0025
A1134280A
6C
R
Date Code
Lot Code
Sample package with part marking
for XC2S50-6PQ208C.
ds001-1_02_090303
DS001-1 (v2.8) June 13, 2008
Product Specification
www.xilinx.com
Module 1 of 4
5
Analogue and Mixed Signal
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