DATASHEET
X40626
64K, 8K x 8 Bit Dual Voltage CPU Supervisor with 64K Serial EEPROM
FEATURES
• Dual voltage monitoring
—V
2Mon
operates independent of V
CC
• Watchdog timer with selectable timeout intervals
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
—User programmable V
TRIP
threshold
—Reset signal valid to V
CC
=1V
• Low power CMOS
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock
™
protection
• 400kHz 2-wire interface
—Slave addressing supports up to 4 devices on
the same bus
FN8119
Rev 0.00
March 28, 2005
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
—14-lead TSSOP
DESCRIPTION
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time-
out interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
BLOCK DIAGRAM
V2FAIL
V2MON
V2 Monitor
Logic
Watchdog Transition
Detector
WP
SDA
Data
Register
Command
Decode &
Control
Logic
V
CC
Threshold
Reset logic
Block Lock Control
Protect Logic
+
V
TRIP2
-
Watchdog
Timer Reset
RESET
Status
Register
Reset &
Watchdog
Timebase
SCL
S0
S1
64KB
EEPROM
Array
V
CC
V
TRIP
+
-
Power-on and
Low Voltage
Reset
Generation
FN8119 Rev 0.00
March 28, 2005
Page 1 of 22
X40626
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the set minimum V
CC
trip point.
RESET is asserted until V
CC
returns to proper operating
level and stabilizes. Four industry standard Vtrip thresholds
are available. However, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom require-
ments or to fine-tune the threshold for applications requir-
ing higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock
™
Protection. The
array is internally organized as 64 bytes per page. The
device features an 2-wire interface and software protocol
allowing operation on an I
2
C bus.
PIN FUNCTION
Pin
1, 4, 6, 13
2
3
5
The device utilizes Intersil’s proprietary Direct Write
™
cell,
providing a minimum endurance of 100,000 page write
cycles and a minimum data retention of 100 years.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S
0
S
1
NC
RESET
NC
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
WP
V2MON
V2FAIL
SCL
SDA
Name
NC
S
0
S
1
RESET
No Internal Connections
Device Select Input
Device Select Input
Function
Reset Output.
RESET is an active LOW, open drain output which goes active whenever V
CC
falls below the minimum V
CC
sense level. It will remain active until V
CC
rises above the mini-
mum V
CC
sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes
active on power-up and remains active for typically 200ms after the power supply
stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This
pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on
this pin. This circuit works independently from the Low V
CC
reset and battery switch circuits.
Connect V2FAIL to VSS when not used.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect V2MON
to V
SS
or V
CC
when not used. There is no hysteresis in the V2MON comparator circuits.
Write Protect.
WP HIGH used in conjunction with WPEN bit prevents writes to the control reg-
ister.
Supply Voltage
7
8
V
SS
SDA
9
10
SCL
V2FAIL
11
V2MON
12
14
WP
V
CC
FN8119 Rev 0.00
March 28, 2005
Page 2 of 22
X40626
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X40626 activates a power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
When V
CC
exceeds the device V
TRIP
threshold value for
t
PURST
(200ms nominal) the circuit releases RESET
allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the V
CC
level
and asserts RESET if supply voltage falls below a preset
minimum V
TRIP
. The RESET signal prevents the micro-
processor from operating in a power fail or brownout
condition. The RESET signal remains active until the
voltage drops below 1V. It also remains active until V
CC
returns and exceeds V
TRIP
for 200ms.
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The micro-
processor must toggle the SDA pin HIGH to LOW peri-
odically, while SCL is HIGH (this is a start bit) prior to the
expiration of the watchdog time-out period to prevent a
RESET signal. The state of two nonvolatile control bits in
the Status Register determine the watchdog timer period.
The microprocessor can change these watchdog bits, or
they may be “locked” by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-progress
communications are terminated. While RESET is active,
no new communications are allowed and no non-volatile
write operation can start. Non-volatile writes in-progress
when RESET goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
CC
/V
2MON
THRESHOLD RESET PROCEDURE
The X40626 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
is not exactly right, or if
higher precision is needed in the V
TRIP
value, the
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvola-
tile control signal.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher or
lower voltage value. It is necessary to reset the trip point
before setting the new value.
The V
CC
and V2MON must be tied together during this
sequence.
To set the new V
TRIP
voltage, start by setting the WEL
bit in the control register, then apply the desired V
TRIP
threshold voltage to the V
CC
pin and the programming
voltage, V
P
, to the WP pin and 2 byte address and 1
byte of “00” data. The stop bit following a valid write
operation initiates the V
TRIP
programming sequence.
Bring WP LOW to complete the operation.
Figure 1. Set V
TRIP
Level Sequence (V
CC
/V
2MON
= desired V
TRIP
values, WP = 12-15V when WEL bit set)
V
P
= 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
WP
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
SDA
A0H
00H
xxH*
*for V
VTRIP2
address is 0DH
for V
TRIP
address is 01H
00H
FN8119 Rev 0.00
March 28, 2005
Page 3 of 22
X40626
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native” volt-
age level. For example, if the current V
TRIP
is 4.4V and
the new V
TRIP
must be 4.0V, then the V
TRIP
must be
reset. When V
TRIP
is reset, the new V
TRIP
is something
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
To reset the new V
TRIP
voltage start by setting the WEL
bit in the control register, apply the desired V
TRIP
thresh-
old voltage to the V
CC
pin and the programming voltage,
V
P
, to the WP pin and 2 byte address and 1 byte of “00”
data. The stop bit of a valid write operation initiates the
V
TRIP
programming sequence. Bring WP LOW to com-
plete the operation.
Figure 2. Reset V
TRIP
Level Sequence (V
CC
/V
2MON
> 3V, WP = 12-15V, WEL bit set)
V
P
= 12-15V
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
WP
0 1 2 3 4 5 6 7
SCL
0 1 2 3 4 5 6 7
SDA
A0H
00H
xxH*
*for V
TRIP2
address is 0FH
for V
TRIP
address is 03H
00H
Figure 3. Sample V
TRIP
Reset Circuit
V
P
4.7K
RESET
V
TRIP
Adj.
1
2
12
3
4
X40626
5
6
9
7
8
14
13
Adjust
µC
Run
SCL
SDA
FN8119 Rev 0.00
March 28, 2005
Page 4 of 22
X40626
Figure 4. V
TRIP
Programming Sequence
V
TRIPX
Programming
Vx = V
CC
, V2MON
Let:
MDE = Maximum Desired Error
No
Desired
V
TRIPX
Present Value
YES
Set V
X
= Desired V
TRIPX
MDE
+
Acceptable
Desired Value
Error Range
MDE
–
Error = Actual - Desired
Execute
Set Higher V
TRIPX
Sequence
New V
X
applied =
Old V
X
applied + | Error |
Execute
Set Higher V
X
Sequence
New V
X
applied =
Old V
X
applied - | Error |
Apply V
CC
and Voltage
> Desired V
TRIPX
to V
X
NO
Decrease V
X
Execute Reset V
TRIPX
Sequence
Output Switches?
YES
Error < MDE
–
Actual V
TRIPX -
Desired V
TRIPX
| Error | < | MDE |
DONE
Error > MDE
+
FN8119 Rev 0.00
March 28, 2005
Page 5 of 22
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