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X40411V8I-B

Description
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8
Categoryaccessories   
File Size888KB,24 Pages
ManufacturerIntersil ( Renesas )
Websitehttp://www.intersil.com/cda/home/
Download Datasheet View All

X40411V8I-B Overview

2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8

X40410, X40411, X40414,
NOT REC
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X40415
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DATASHEET
FN8116
Rev 0.00
March 28, 2005
4kbit EEPROM Dual Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power-on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect none or 1/2 of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
BLOCK DIAGRAM
Watchdog Timer
and
Reset Logic
• Monitor Voltages: 5V to 0.9V
• Memory Security
• Independent Core Voltage Monitor
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Computers
—Network Servers
DESCRIPTION
The X40410/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, and Block Lock
pro-
tect serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
SDA
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
EEPROM
Array
WDO
SCL
V
CC
(V1MON)
+
User Programmable
V
TRIP1
User Programmable
V
TRIP2
-
+
-
V
CC
or
V2MON
Power-on,
Low Voltage
Reset
Generation
RESET
X40410/14
RESET
X40411/15
V2MON
V2FAIL
*X40410/11= V2MON*
X40414/15 = V
CC
FN8116 Rev 0.00
March 28, 2005
Page 1 of 24
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