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550PG074M250DGR

Description
CMOS Output Clock Oscillator, 74.25MHz Nom, ROHS COMPLIANT PACKAGE-6
CategoryPassive components    oscillator   
File Size231KB,14 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

550PG074M250DGR Overview

CMOS Output Clock Oscillator, 74.25MHz Nom, ROHS COMPLIANT PACKAGE-6

550PG074M250DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Other featuresCOMPLEMENTARY OUTPUT; TRI-STATE; ENABLE/DISABLE FUNCTION; TAPE AND REEL
Maximum control voltage3.3 V
Minimum control voltage
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate375 ppm
frequency stability20%
JESD-609 codee4
linearity10%
Manufacturer's serial numberSI550
Installation featuresSURFACE MOUNT
Nominal operating frequency74.25 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Output load15 pF
physical size7.0mm x 5.0mm x 1.85mm
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Si550
R
EVISION
D
V
O L TA G E
- C
O N T R O L L E D
C
R Y S TA L
O
S C I L L A T O R
(VCXO)
10 MH
Z T O
1.4 G H
Z
Features
Available with any-rate output
frequencies from 10 to 945 MHz
and selected frequencies to
1.4 GHz
3rd generation DSPLL
®
with
superior jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Lead-free/RoHS-compliant
Si5602
Ordering Information:
See page 8.
Applications
SONET/SDH
xDSL
10 GbE LAN/WAN
Low-jitter clock generation
Optical modules
Clock and data recovery
Pin Assignments:
See page 7.
(Top View)
V
C
1
2
3
6
5
4
V
DD
Description
The Si550 VCXO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry to
provide a low-jitter clock at high frequencies. The Si550 is available with
any-rate output frequency from 10 to 945 MHz and selected frequencies to
1400 MHz. Unlike traditional VCXOs, where a different crystal is required for
each output frequency, the Si550 uses one fixed crystal to provide a wide
range of output frequencies. This IC-based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In
addition, DSPLL clock synthesis provides superior supply noise rejection,
simplifying the task of generating low-jitter clocks in noisy environments
typically found in communication systems. The Si550 IC-based VCXO is
factory-configurable for a wide variety of user specifications, including
frequency, supply voltage, output format, tuning slope, and temperature
stability. Specific configurations are factory programmed at time of shipment,
thereby eliminating the long lead times associated with custom oscillators.
OE
GND
CLK–
CLK+
Functional Block Diagram
V
DD
CLK–
CLK+
Fixed
Frequency
XO
Any-rate
10-1400 MHz
DSPLL
®
Clock Synthesis
ADC
Vc
OE
GND
Rev. 0.6 6/07
Copyright © 2007 by Silicon Laboratories
Si550
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