MT55L512Y32FT-8.8 datasheet, PDF

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MT55L512Y32FT-8.8: DescriptionZBT SRAM, 512KX32, 6.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100; Categorystorage storage; File Size468KB，34 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT55L512Y32FT-8.8 Overview

ZBT SRAM, 512KX32, 6.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100

MT55L512Y32FT-8.8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Micron Technology
Parts packaging code	QFP
package instruction	PLASTIC, MS-026BHA, TQFP-100
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	6.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	113 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
length	20 mm
memory density	16777216 bit
Memory IC Type	ZBT SRAM
memory width	32
Number of functions	1
Number of terminals	100
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.03 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb ZBT

SRAM

Features

• High frequency and 100 percent bus utilization

• Single 3.3V ±5 percent or 2.5V ±5 percent power

supply

• Separate 3.3V ±5 percent or 2.5V ±5 percent isolated

output buffer supply (V

• Advanced control logic for minimum control signal

interface

• Individual byte write controls may be tied LOW

• Single R/W# (read/write) control pin/ball

• CKE# pin/ball to enable clock and suspend

operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

I/Os, and control signals

• Internally self-timed, fully coherent write

• Internally self-timed, registered outputs to

eliminate the need to control OE#

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature (optional)

• Pin and ball/function compatibility with 2Mb, 4Mb,

and 8Mb ZBT SRAM

MT55L1MY18F, MT55V1MV18F,

MT55L512Y32F, MT55V512V32F,

MT55L512Y36F, MT55V512V36F

3.3V V

, 3.3V or 2.5V I/O; 2.5V V

, 2.5V I/O

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

Figure 2: 165-Ball FBGA

JEDEC-Standard MS-216 (Var. CAB-1)

Options

• Timing (Access/Cycle/MHz)

6.5ns/8.8ns/113 MHz

7.5ns/10ns/100 MHz

8.5ns/11ns/90 MHz

• Configurations

3.3V V

, 3.3V or 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

2.5V V

, 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

• Packages

100-pin TQFP

165-ball, 13mm x 15mm FBGA

• Operating Temperature Range

Commercial (0ºC

+70ºC)

Industrial (-40ºC

+85ºC)

NOTE:

TQFP

Marking

-8.8

-10

-11

Part Number Example:

MT55L1MY18F

MT55L512Y32F

MT55L512Y36F

MT55V1MV18F

MT55V512V32F

MT55V512V36F

None

MT55L512Y36FT-11

General Description

The Micron

Zero Bus Turnaround

™

(ZBT

) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,

512K x 32, or 512K x 36 SRAM core with advanced syn-

chronous peripheral circuitry and a 2-bit burst

counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles for

READ to WRITE, or WRITE to READ, transitions. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input (CLK).

The synchronous inputs include all addresses, all data

inputs, chip enable (CE#), two additional chip enables

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact Factory for availability of Industrual Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

Table 1:

SYMBOL

ADV/LD#

TQFP Pin Descriptions

TYPE

Input

DESCRIPTION

Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal

burst counter, controlling burst access after the external address is loaded. When ADV/LD# is

HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be

written when a WRITE cycle is active and must meet the setup and hold times around the

rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are

associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#

controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW).

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the

device. When CKE is HIGH, the device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet setup and hold times around the rising

edge of CLK.

Clock: This signal registers the address, data, chip enables, byte write enables, and burst

control inputs on its rising edge. All synchronous inputs must meet setup and hold times

around the clock’s rising edge.

Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or

HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.

LBO# is the JEDEC-standard term for MODE.

Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#

is the JEDEC-standard term for OE#.

Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only

means for determining READs and WRITEs. READ cycles may not be converted into WRITEs

(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE

operations and must meet the setup and hold times around the rising edge of CLK. Full bus-

width WRITEs occur if all byte write enables are LOW.

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of

the address field and set the internal burst counter if burst is desired.

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This pin has an internal pull-down and can be left unconnected.

SRAM Data I/Os: Byte “a” is associated with DQa pins; byte “b” is associated with DQb pins;

byte “c” is associated with DQc pins; byte “d” is associated with DQd pins. Input data must

meet setup and hold times around the rising edge CLK.

No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18

version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity

is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for

range.

Ground: GND.

Micron Technology, Inc., reserves the right to change products or specifications without notice.

BWa#

BWb#

BWc#

BWd#

CE#

CE2#

Input

CE2

Input

CKE#

Input

CLK

Input

MODE (LBO#)

Input

OE# (G#)

R/W#

Input

SA0

SA1

Input

DQa

DQb

DQc

DQd

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

Input/

Output

I/O

Supply

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

MT55L1MY18F_16_D.fm – Rev. D, Pub. 2/03

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