EEWORLDEEWORLDEEWORLD

Part Number

Search

C1632C103K4RAC

Description
ISOLATED C NETWORK, 50V, X7R, 0.01uF, SURFACE MOUNT, CHIP-8
CategoryPassive components   
File Size907KB,7 Pages
ManufacturerKEMET
Websitehttp://www.kemet.com
Download Datasheet Parametric View All

C1632C103K4RAC Online Shopping

Suppliers Part Number Price MOQ In stock  
C1632C103K4RAC - - View Buy Now

C1632C103K4RAC Overview

ISOLATED C NETWORK, 50V, X7R, 0.01uF, SURFACE MOUNT, CHIP-8

C1632C103K4RAC Parametric

Parameter NameAttribute value
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
negative deviation10 %
positive deviation10 %
Rated DC voltage urdc50 V
Processing package descriptionCHIP, ROHS COMPLIANT
Lead-freeYes
EU RoHS regulationsYes
stateACTIVE
terminal coatingMATTE TIN
Installation featuresSURFACE MOUNT
Manufacturer SeriesC1632
capacitance0.0100 uF
packaging shapeRECTANGULAR PACKAGE
Capacitor typeISOLATED C NETWORK
Terminal spacing0.8000 mm
Terminal shapeWRAPAROUND
Number of components1
Number of functions4
Number of terminals8
Temperature Coefficient15%
Temperature characteristic codeX7R
CERAMIC CAPACITOR ARRAY
FEATURES
Four individual capacitors inside
one 1206 monolithic structure
Saves board and inventory space
One placement instead of four - less costly
Easier to handle and solder than 4 smaller chips
Tape and reel per EIA 481-1
RoHS Compliant
CAPACITOR OUTLINE DRAWING
T
L
CL
BW
W
P/2
Ref
P
BW1
TABLE 1
EIA DIMENSIONS – MILLIMETERS (INCHES)
Size
Code
1632
Length
L
3.2 (0.126)
±
0.2 (0.008)
Width
W
1.6 (.063)
±
0.2 (.008)
Thickness
T (max.)
0.7 - 1.35
(0.027 - 0.053)
Bandwidth
BW
Bandwidth
BW1
Pitch
P
0.40 (0.016)
0.1 - 0.5
0.8 (0.031)
±
0.2 (0.008) (0.004 - 0.020)
±
0.1 (0.004)
CERAMIC ARRAY ORDERING INFORMATION
C
1632
C
103
K
5
R
A
C
END METALLIZATION
C-Standard
(Tin-plated nickel barrier)
FAILURE RATE LEVEL
A- Not Applicable
TEMPERATURE CHARACTERISTIC
Designated by Capacitance
Change Over T
emperature Range
G – C0G (NP0) (±30 PPM/°C)
R – X7R (±15%)
VOLTAGE
5 = 50v; 3 = 25v; 4 = 16v; 8=10v
CERAMIC
EIA SIZE CODE
Ceramic chip array
SPECIFICATION
C - Standard
CAPACITANCE CODE
Expressed in Picofarads (pF)
First two digits represent significant figures.
Third digit specifies number of zeros. (Use 9
for 1.0 thru 9.9pF (Example: 2.2pF = 229
.
CAPACITANCE TOLERANCE
K –
±10%:
M –
±20%
Standard Tolerances
Contact factory for any special requirements.
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
85
Ceramic Surface Mount
Notes:
1. Metric is controlling - English for reference only.
2. Pitch (P) tolerances are non-cumulative along the package.
3. Thickness (T) depends on capacitance.

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 805  1227  2832  1519  60  17  25  58  31  2 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号