4 Megabit High Speed CMOS SRAM
DPS128X32CV3/DPS128X32BV3
DESCRIPTION:
The DPS128X32CV3/DPS128X32BV3 ‘’VERSA-STACK’’ module is
a revolutionary new high speed memory subsystem using Dense-Pac
Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC)
mounted on a co-fired ceramic substrate. It offers 4 Megabits of
SRAM in a package envelope of 1.090 x 1.090 x 0.252 inches.
The DPS128X32CV3/DPS128X32BV3 contains four individual
128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs
making the module suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher
board density of memory than available with conventional
through-hole, surface mount, module, or hybrid techniques.
The DPS128X32BV3 has one active low Chip Enable (CE) and while
the DPS128X32CV3 an active low Chip Enable (CE) and an active
high Select Line (SEL).
By using SLCCs, the ‘’Versa-Stack’’ family of modules offer a
higher board density of memory than available with
conventional through-hole, surface mount or hybrid
techniques.
FEATURES:
•
•
•
•
•
•
•
•
•
Organizations Available:
128K x 32, 256K x 16, or 512K x 8
Access Times:
20*, 25, 30, 35, 45ns
Fully Static Operation
- No clock or refresh required
Low Power Dissipation:
8.0mW (typ.) Full Standby
0.8W (typ.) Operating (x8)
Single +5V Power Supply,
±10%
Tolerance
TTL Compatible
Common Data Inputs and Outputs
Low Data Retention Current:
140µA typ. (2.0V)
66-Pin PGA ‘’VERSA-STACK’’
Package
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM
*
Commercial only.
PIN NAMES
A0 - A16
I/O0 - I/O31
CE0 - CE3
SEL
WE0 - WE1
OE
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Low Chip Enables
High Chip Enable
Write Enables
Output Enable
Power (+5V)
Ground
No Connect
NOTE:
SEL applies to the DPS128X32CV3 only, No Connect for the DPS128X32BV3 version.
30A044-24
REV. F
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPS128X32CV3/DPS128X32BV3
RECOMMENDED OPERATING RANGE
3
Dense-Pac Microsystems, Inc.
TRUTH TABLE
Mode
Not Selected
Not Selected
D
OUT
Disable
Read
Write
H = HIGH
SEL
L
X
H
H
H
CE
X
H
L
L
L
WE
X
X
H
H
L
Supply
OE I/O Pin Current
X High-Z Standby
X High-Z Standby
H High-Z Active
L
D
OUT
Active
X
D
IN
Active
X = Don’t Care
Symbol
Characteristic
Min. Typ.
Max. Unit
V
DD
Supply Voltage
4.5 5.0
5.5
V
V
IH
Input HIGH Voltage 2.2
V
DD
+0.3 V
V
IL
Input LOW Voltage -0.5
2
0.8
V
M -55 +25 +125
Operating
o
T
A
I
-40 +25 +85
C
Temperature
C
0 +25 +70
L = LOW
NOTE:
SEL applies to DPS128X32CV3 version only.
DC OUTPUT CHARACTERISTICS
Symbol
Parameter
V
OH
HIGH Voltage
V
OL
LOW Voltage
Conditions Min. Max. Unit
I
OH
= -4.0mA 2.4
V
I
OL
=8.0mA
0.4 V
CAPACITANCE
4
: T
A
= 25
°
C, F = 1.0MHz
Symbol
Parameter
C
ADR
Address Input
C
CE
Chip Enable
Active High
C
SEL
Chip Select
C
WE
Write Enable
C
OE
Output Enable
C
I/O
Data Input/Output
Max.
50
20
50
25
50
20
Unit
Condition
ABSOLUTE MAXIMUM RATINGS
Symbol
T
STC
T
BIAS
V
DD
V
I/O
3
Parameter
Value
Storage Temperature
-65 to +150
Temperature Under Bias
-55 to +125
1
Supply Voltage
-0.5 to +7.0
1
Input/Output Voltage
-0.5 to V
DD
+0.5
Unit
°C
°C
°C
V
pF
V
IN2
= 0V
NOTE:
C
SEL
applies to DPS128X32CV3 version only.
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
I
IN
I
OUT
I
CC
I
SB1
I
SB2
I
DR3
I
DR2
V
OL
V
OH
Characteristics
Input
Leakage Current
Output
Leakage Current
Operating
Supply Current
Full Standby
Supply Current
Standby Current (TTL)
Data Retention
Supply Current
(3V)
Data Retention
Supply Current
(2V)
Output Low Voltage
Output High Voltage
Test Conditions
V
IN
= 0V to V
DD
V
I/O
= 0V to V
DD
,
CE or OE = V
IH
, or WE = V
IL
Cycle=min., Duty=100%
I
OUT
= 0mA
X8
X16
X32
Typ.
(†)
-
-
175
250
400
1.6
100
0.28
0.14
-
-
C
Min.
Max.
Min.
I
Max.
Min.
M
Max.
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
-20
-10
+20
+10
230
340
560
20
120
1.60
1.00
0.4
-20
-10
+20
+10
245
350
560
20
140
2.40
1.60
0.4
-20
-10
+20
+10
265
390
640
40
140
8.00
7.20
0.4
V
IN
≥
V
DD
-0.2V or
V
IN
≤
V
SS
+0.2V
CE = V
IH
V
DR
= 3V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
V
DR
= 2V, CE
≥
V
DR
-0.2V,
(or SEL
≤
0.2V, V
IN
≥
V
DD
-0.2V
or V
IN
≤
+0.2V)
I
OUT
= 8.0mA
I
OUT
= -4.0mA
2.4
2.4
2.4
† Typical measurements made at +25
o
C, Cycle = min., V
DD
= 5.0V.
2
30A044-24
REV. F
Dense-Pac Microsystems, Inc.
DPS128X32CV3/DPS128X32BV3
Data Retention AC Characteristics
Symbol
V
DR
V
CDR
t
R
Parameter
V
DD
for Data
Retention
Chip Disable to
Data Retention Time
Operation Recovery Time
Test Conditions
CE
≥
V
DR
-0.2V, (SEL
≥
V
DR
-0.2V,
or V
IN
≤
V
DR
-0.2V or V
IN
≤
0.2V)
See Data Retention Waveform
See Data Retention Waveform
8
Min.
2.0
0
5
Typ.
-
-
-
Max.
-
-
-
Unit
V
ns
ms
NOTE:
Test Conditions in parenthesis apply to DPS128X32CV3 version only.
DATA RETENTION WAVEFORM:
CE Controlled.
V
DD
4.5V
2.3V
V
DR1
CE
0V
CE
≥
V
DD
-0.2V
DATA RETENTION WAVEFORM:
SEL Controlled. (Applies to DPS128X32CV3 only)
V
DD
4.5V
SEL
V
DR2
0.4V
0V
SEL
≤
-0.2V
30A044-24
REV. F
3
DPS128X32CV3/DPS128X32BV3
OUTPUT LOAD
Load
1
2
C
L
30pF
5pF
Parameters Measured
except t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
,
and t
WHZ
t
LZ1
, t
LZ2
, t
HZ1
, t
HZ2
, t
OHZ
, t
OLZ
, and
t
WHZ
Dense-Pac Microsystems, Inc.
Figure 1.
Output Load
* Including Probe and Jig Capacitance.
+5V
480Ω
NOTE:
t
LZ2
and t
HZ2
apply to DPS128X32CV3 version only.
AC TEST CONDITIONS
Input Pulse Levels
Input Pulse Rise and Fall Times
Input and Output
Timing Reference Levels
0V to 3.0V
5ns
1.5V
D
OUT
C
L
*
255Ω
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol
1
2
3
4
5
6
7
8
9
10
11
12
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
t
OH
Parameter
Read Cycle Time
Address Access Time
CE to Output Valid
SEL to Output Valid
Output Enable to Output Valid
CE to Output in LOW-Z
4, 5
SEL to Output in LOW-Z
4, 5
Output Enable to Output in LOW-Z
4, 5
CE to Output in HIGH-Z
4, 5
SEL to Output in HIGH-Z
4, 5
Output Enable to Output in HIGH-Z
4, 5
Output Hold from Address Change
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
8
3
3
0
10
10
8
3
25
25
25
25
10
3
3
0
12
12
10
3
30
30
30
30
15
3
3
0
15
15
15
3
35
35
35
35
20
3
3
0
20
20
20
3
45
45
45
45
25
3
3
0
25
25
25
3
* Available in Commercial Only.
NOTE:
t
CO2
, t
LZ2
and t
HZ2
apply to DPS128X32CV3 version only.
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE
6, 7
: Over operating ranges
No. Symbol
13
14
15
16
17
18
19
20
21
22
t
WC
t
AW
t
CW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Parameter
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-Up Time **
Write Pulse Width
Write Recovery Time
Write Enable to Output in HIGH-Z
4, 5
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
20ns*
Min.
Max.
25ns
Min.
Max.
30ns
Min.
Max.
35ns
Min.
Max.
45ns
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
15
15
0
15
0
8
12
0
3
25
20
20
0
20
0
10
15
0
3
30
25
25
0
25
0
12
15
0
3
35
30
30
0
30
0
15
20
0
3
45
40
40
0
35
0
20
25
0
3
* Available in Commercial Only.
** Valid for both Read and Write Cycles.
4
30A044-24
REV. F
Dense-Pac Microsystems, Inc.
DPS128X32CV3/DPS128X32BV3
READ CYCLE
ADDRESS
CE
SEL
OE
DATA I/O
WRITE CYCLE 1:
CE Controlled.
8
ADDRESS
CE
WE
DATA IN
DATA OUT
30A044-24
REV. F
5
FPGA/CPLD
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