P4C1982-25CM datasheet, PDF - EEWORLD Datasheet

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P4C1982-25CM: DescriptionStandard SRAM, 16KX4, 25ns, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28; Categorystorage storage; File Size332KB，13 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1982-25CM Overview

Standard SRAM, 16KX4, 25ns, CMOS, CDIP28, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-28

P4C1982-25CM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Maximum access time	25 ns
JESD-30 code	R-CDIP-T28
JESD-609 code	e0
memory density	65536 bit
Memory IC Type	STANDARD SRAM
memory width	4
Number of functions	1
Number of terminals	28
word count	16384 words
character code	16000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	16KX4
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	5.715 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm

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P4C1981/P4C1981L, P4C1982/P4C1982L

ULTRA HIGH SPEED 16K x 4

CMOS STATIC RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25 ns (Commercial)

– 12/15/20/25/35 ns (Industrial)

– 15/20/25/35/45 ns (Military)

Low Power Operation (Commercial/Military)

Output Enable and Dual Chip Enable Functions

5V ± 10% Power Supply

Data Retention with 2.0V Supply, 10 µA Typical

Current (P4C1981L/1982L Military)

Separate Inputs and Outputs

– P4C1981/L Input Data at Outputs during Write

– P4C1982/L Outputs in High Z during Write

Fully TTL Compatible Inputs and Outputs

Standard Pinout (JEDEC Approved)

– 28-Pin 300 mil DIP, SOJ

– 28-Pin 350 x 550 mil LCC

– 28-Pin CERPACK

DESCRIPTION

The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)

ultra high-speed static RAMs similar to the P4C198, but

with separate data I/O pins. The P4C1981/L feature a

transparent write operation when

is low; the outputs

of the P4C1982/L are in high impedance during the write

cycle. All devices have low power standby modes. The

RAMs operate from a single 5V ± 10% tolerance power

supply. With battery backup, data integrity is maintained

for supply voltages down to 2.0V. Current drain is

typically 10 µA from 2.0V supply.

Access times as fast as 10 nanoseconds are available,

permitting greatly enhanced system operating speeds.

CMOS is used to reduce power consumption. For the

P4C1982L and P4C1981L, power is only 5.5 mW standby

with CMOS input levels.

The P4C1981/L and P4C1982/L are available in 28-pin 300

mil DIP and SOJ, 28-pin 350x550 mil LCC and a 28-pin

CERPACK package providing excellent board level den-

sities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P5, C5, D5-2), SOJ (J5)

CERPACK (F4) SIMILAR

P4C1981/ 1982

LCC (L5)

Document #

SRAM114

REV B

Revised August 2006

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