SAA7102; SAA7103
Digital video encoder
Rev. 04 — 18 January 2006
Product data sheet
1. General description
The SAA7102; SAA7103 is used to encode PC graphics data at maximum 800
×
600
resolution to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and
interlacer ensures properly sized and flicker-free TV display as CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals
together with a TTL composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the
RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor
at maximum 800
×
600 resolution/60 Hz (PIXCLK < 45 MHz).
The device includes a sync/clock generator and on-chip DACs.
2. Features
■
Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for
TV output from a PC
■
27 MHz crystal-stable subcarrier generation
■
Maximum graphics pixel clock 45 MHz at double edged clocking, synthesized on-chip
or from external source
■
Up to 800
×
600 graphics data at 60 Hz or 50 Hz with programmable underscan range.
■
Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,
C
B
), VBS (GREEN, CVBS) and C (RED, C
R
) (signals in parenthesis are optional); all at
10-bit resolution
■
Non-Interlaced (NI) C
B
-Y-C
R
or RGB input at maximum 4 : 4 : 4 sampling
■
Downscaling from 1 : 1 to 1 : 2 and up to 20 % upscaling
■
Optional interlaced C
B
-Y-C
R
input of Digital Versatile Disc (DVD) signals
■
Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with
maximum 45 MHz)
■
3
×
256 bytes RGB Look-Up Table (LUT)
■
Support for hardware cursor
■
Programmable border color of underscan area
■
On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)
■
Fast I
2
C-bus control port (400 kHz)
■
Encoder can be master or slave
■
Programmable horizontal and vertical input synchronization phase
■
Programmable horizontal sync output phase
■
Internal Color Bar Generator (CBG)
■
Optional support of various Vertical Blanking Interval (VBI) data insertion
Philips Semiconductors
SAA7102; SAA7103
Digital video encoder
■
Macrovision Pay-per-View copy protection system rev. 7.01 and rev. 6.1 as option; this
applies to the SAA7102 only
■
Power-save modes
■
Joint Test Action Group (JTAG) Boundary Scan Test (BST)
■
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
■
QFP44 and LBGA156 packages
■
Same footprint as SAA7108E; SAA7109E
3. Quick reference data
Table 1:
Symbol
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
Quick reference data
Parameter
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog CVBS output signal
voltage for a 100/100 color bar
at 75/2
Ω
load
(peak-to-peak value)
load resistance
low frequency integral linearity
error of DACs
low frequency differential
linearity error of DACs
ambient temperature
Conditions
Min
3.15
3.0
1
1
-
Typ
3.3
3.3
110
70
1.23
Max
3.45
3.6
140
90
-
Unit
V
V
mA
mA
V
TTL compatible
R
L
ILE
lf(DAC)
DLE
lf(DAC)
T
amb
-
-
-
0
37.5
-
-
-
-
±3
±1
70
Ω
LSB
LSB
°C
4. Ordering information
Table 2:
Ordering information
Package
Name
SAA7102E
SAA7103E
SAA7102H
SAA7103H
QFP44
LBGA156
Description
plastic low profile ball grid array package; 156 balls;
body 15
×
15
×
1.05 mm
plastic quad flat package; 44 leads (lead length
1.3 mm); body 10
×
10
×
1.75 mm
Version
SOT700-1
SOT307-2
Type number
SAA7102_SAA7103_4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 18 January 2006
2 of 84
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SAA7102_SAA7103_4
Product data sheet
V
DDD2
RSET
DUMP
33
32
38
8
7
6
31
37
TDI
TCK
TMS
TRST
TDO
V
SSD1
9
40
39
36
29
V
SSD2
V
DDA1
V
DDA2
V
SSA1
RGB LUT
(OR BYPASS)
MATRIX
(OR BYPASS)
CURSOR
INSERTION
RGB TO Y-C
B
-C
R
HORIZONTAL
SCALER
FIFO
VERTICAL
SCALER AND
ANTI-FLICKER
FILTER
30
VIDEO
ENCODER
TRIPLE
DAC
28
27
26
25
I
2
C-BUS
CONTROL
OSCILLATOR/
DTO
TIMING
GENERATOR
BLUE_CB_CVBS
GREEN_VBS_CVBS
RED_CR_C
HSM_CSYNC
VSM
5. Block diagram
V
DDD1
Philips Semiconductors
10
PD11 to
PD0
4 to 1,
44 to 41,
16 to 19
INPUT
FORMATTER
PIXCLKI
15
DECIMATOR
4 : 4 : 4 to 4 : 2 : 2
(OR BYPASS)
Rev. 04 — 18 January 2006
SAA7102H
SAA7103H
23
14
21
XTALI
VSVGC
TTX_SRES
FSVGC
27 MHz
CBO
TTXRQ_XCLKO2
XTALO
HSVGC
SDA
SCL
RESET
35
34
13
22
24
12
11
5
BORDER
GENERATOR
PIXCLKO
20
CGC
LOW-PASS
mhb963
SAA7102; SAA7103
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Digital video encoder
3 of 84
Fig 1. Block diagram (SAA7102H and SAA7103H)
DSP and ARM Processors
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