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PC7410MGU500NE

Description
RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1023KB,57 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

PC7410MGU500NE Overview

RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360, 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360

PC7410MGU500NE Parametric

Parameter NameAttribute value
MakerAtmel (Microchip)
Parts packaging codeBGA
package instructionBGA,
Contacts360
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Address bus width32
bit size32
boundary scanYES
maximum clock frequency133 MHz
External data bus width64
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeS-CBGA-B360
length25 mm
low power modeYES
Number of terminals360
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Maximum seat height3.2 mm
speed500 MHz
Maximum supply voltage1.55 V
Minimum supply voltage1.45 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
width25 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
PC7410
PowerPC 7410 RISC Microprocessor
Datasheet
Features
22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)
917MIPS at 500 MHz
Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)
Seven Selectable Core-to-L2 Frequency Divisors
Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)
Selectable L2 interface of 1.8V or 2.5V
P
D
Typical 5.3W at 500 MHz, Full Operating Conditions
Nap, Doze and Sleep Modes for Power Saving
Superscalar (Four Instructions fetched per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 hexabytes (2
52
)
64-bit Data and 32-bit Address Bus Interface
32 KB Instruction and Data Cache
Eight Independent Execution Units and Three Register Files
Write-back and Write-through Operations
f
INT
Max = 450 MHz 500 MHz
f
BUS
Max = 133 MHz
Description
The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruc-
tion Set Computer (RISC) architecture. It is fully JTAG-compliant.
The PC7410 maintains some of the characteristics of G3 microprocessors:
The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units
The microprocessor provides four software controllable power-saving modes and a thermal assist unit management
The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache
interface with on-chip L2 tags
In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro-
tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec
®
technology
instruction set.
New features have been developed to make latency equal for double-precision and single-precision floating-point opera-
tions involving multiplication. Additionally, in memory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-
bandwidth MPX bus interface.
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.
Visit our website: www.e2v.com
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