DRAM MODULE
Preliminary
M53620400DW0/DB0
M53620410DW0/DB0
M53620400DW0/DB0 & M53620410DW0/DB0 with Fast Page Mode
4M x 36 DRAM SIMM using 4Mx4 and 16M Quad CAS, 4K/2K Refresh, 5V
GENERAL DESCRIPTION
The Samsung M5362040(1)0D is a 4Mx36bits Dynamic RAM
high density memory module. The Samsung M5362040(1)0D
consists of eight CMOS 4Mx4bits DRAMs in 24-pin SOJ pack-
age and one CMOS 4Mx4 bit Quad CAS DRAM in 28-pin SOJ
package mounted on a 72-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM. The M5362040(1)0D is a Single In-line
Memory Module with edge connections and is intended for
mounting into 72 pin edge connector sockets.
FEATURES
• Part Identification
- M53620400DW0-C(4096 cycles/64ms Ref, SOJ, Solder)
- M53620400DB0-C(4096 cycles/64ms Ref, SOJ, Gold)
- M53620410DW0-C(2048 cycles/32ms Ref, SOJ, Solder)
- M53620410DB0-C(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode Operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
PERFORMANCE RANGE
Speed
-50
-60
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
90ns
110ns
• JEDEC standard PDPin & pinout
• PCB : Height(1000mil), single sided component
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
Res(RAS1)
RAS0
DQ26
DQ8
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A11
A0 - A10
DQ0 - DQ35
W
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs(4K Ref)
Address Inputs(2K Ref)
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
Vss
NC
Vss
Vss
60NS
Vss
NC
NC
NC
* Pin connection changing available
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
* NOTE : A11 is used for only M53620400DW0/DB0(4K
ref.)
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
CAS0
RAS0
CAS
RAS
OE
DQ0
DQ1
U0
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
U1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
Preliminary
M53620400DW0/DB0
M53620410DW0/DB0
DQ0-DQ3
W
CAS
RAS
OE
DQ4-DQ7
W
CAS1
CAS
RAS
OE
U2
W
DQ9-DQ12
CAS
RAS
OE
U3
W
DQ13-DQ16
CAS2
CAS
RAS
OE
W
DQ0
U4
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ0
DQ1
DQ2
A0-
A11(A10) DQ3
DQ18-DQ21
CAS
RAS
OE
U5
W
DQ22-DQ25
CAS3
CAS
RAS
OE
U6
W
DQ27-DQ30
CAS
RAS
OE
U7
W
DQ31-DQ34
CAS0
CAS1
CAS2
CAS3
RAS
OE W
W
A0-A11(A10)
Vcc
U8
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
A0-
A11(A10)
.1 or .22uF Capacitor
for each DRAM
Vss
To all DRAMs
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
Preliminary
M53620400DW0/DB0
M53620410DW0/DB0
Rating
-1 to +7.0
-1 to +7.0
-55 to +150
9
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
*1 : V
CC
+2.0V/20ns, Pulse width is measured at V
CC
.
*2 : -2.0V/20ns, Pulse width is measured at V
SS
.
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+1
*1
0.8
Unit
V
V
V
V
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-50
-60
Don′t care
-50
-60
-50
-60
Don′t care
-50
-60
Don′t care
Don′t care
M53620400DW0/DB0
Min
-
-
M53620410DW0/DB0
Min
-
-
Max
810
720
18
810
720
720
630
9
810
720
45
5
-
0.4
Max
990
900
18
990
900
810
720
9
990
900
45
5
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-45
-5
2.4
-
-
-
-
-
-
-
-
-
-45
-5
2.4
-
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: Fast Page Mode Current * (RAS=V
IL
, CAS Address cycling :
t
PC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I
I(L)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
I
O(L)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -5mA)
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one page mode cycle,
t
PC
.
DRAM MODULE
CAPACITANCE
(T
A
= 25°C, V
CC
=5V, f = 1MHz)
Item
Input capacitance[A0-A11(A10)]
Input capacitance[W]
Input capacitance[RAS0]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-35]
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
DQ
Min
-
-
-
-
-
Preliminary
M53620400DW0/DB0
M53620410DW0/DB0
Max
65
80
80
40
25
Unit
pF
pF
pF
pF
pF
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, Output loading CL=100pF
Parameter
Random read or write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
Data-in hold time
Refresh period (4K Ref)
Refresh period (2K Ref)
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
Symbol
-50
Min
90
50
13
25
0
0
3
30
50
13
50
13
20
15
5
0
10
0
10
25
0
0
0
10
10
13
13
0
10
64
32
0
5
10
5
0
5
10
5
10K
37
25
10K
13
50
0
0
3
40
60
15
60
15
20
15
5
0
10
0
10
30
0
0
0
10
10
15
15
0
15
64
32
10K
45
30
10K
15
50
Max
Min
110
60
15
30
-60
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
7
9
9
8
8
4
10
3,4
3,4,5
3,10
3
6
2
Note
t
RC
t
RAC
t
CAC
t
AA
t
CLZ
t
OFF
t
T
t
RP
t
RAS
t
RSH
t
CSH
t
CAS
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
RCS
t
RCH
t
RRH
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
REF
t
REF
t
WCS
t
CSR
t
CHR
t
RPC
DRAM MODULE
AC CHARACTERISTICS
(0°C≤T
A
≤70°C,
V
CC
=5.0V±10%. See notes 1,2.)
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.4/0.4V, Output loading CL=100pF
Parameter
Access time from CAS precharge
Fast page mode cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Hold time CAS low to CAS high
Symbol
-50
Min
35
10
50
10
10
5
200K
Max
30
40
10
60
10
10
5
Min
Preliminary
M53620400DW0/DB0
M53620410DW0/DB0
-60
Max
35
Unit
ns
ns
ns
Note
3
t
CPA
t
PC
t
CP
t
RASP
t
WRP
t
WRH
t
CLCH
200K
ns
ns
ns
ns
11
NOTES
1. An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. V
IH
(min) and V
IL
(max) are reference levels for measuring
timing of input signals. Transition times are measured
between V
IH
(min) and V
IL
(max) and are assumed to be 5ns
for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
5. Assumes that
t
RCD
≥
t
RCD
(max).
6. This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
7.
t
WCS
is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
8. Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
9. These parameter are referenced to the CAS leading edge in
early write cycles.
10. Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
11. In order to hold the address latched by the first CAS going
low, the parameter
t
CLCH
must be met.
京公网安备 11010802033920号
EEWORLD
