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MT55L128V32P1F-10

Description
ZBT SRAM, 128KX32, 5ns, CMOS, PBGA165, FBGA-165
Categorystorage    storage   
File Size366KB,26 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT55L128V32P1F-10 Overview

ZBT SRAM, 128KX32, 5ns, CMOS, PBGA165, FBGA-165

MT55L128V32P1F-10 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeBGA
package instructionTBGA,
Contacts165
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time5 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PBGA-B165
JESD-609 codee0
length15 mm
memory density4194304 bit
Memory IC TypeZBT SRAM
memory width32
Humidity sensitivity level3
Number of functions1
Number of terminals165
word count131072 words
character code128000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX32
Package body materialPLASTIC/EPOXY
encapsulated codeTBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width13 mm
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
4Mb
ZBT
®
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 6ns, 7.5ns and 10ns
Single +3.3V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
Automatic power-down
165-pin FBGA package
100-pin TQFP package
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
3.3V V
DD
, 3.3V or 2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Package
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-6
-7.5
-10
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
MT55L256L18P1
MT55L128L32P1
MT55L128L36P1
MT55L256V18P1
MT55L128V32P1
MT55L128V36P1
T
F*
None
IT
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
(ZBT
®
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utiliza-
tion, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
MT55L256L18P1T-10
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
1
©2003, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
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