CY28373OC datasheet, PDF - EEWORLD Datasheet

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CY28373OC: DescriptionProcessor Specific Clock Generator, 200MHz, CMOS, PDSO56, SSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size137KB，20 Pages; ManufacturerCypress Semiconductor

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CY28373OC Overview

Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, SSOP-56

CY28373OC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	SSOP
package instruction	SSOP-56
Contacts	56
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G56
JESD-609 code	e0
length	18.415 mm
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	200 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP56,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Master clock/crystal nominal frequency	14.318 MHz
Certification status	Not Qualified
Maximum seat height	2.794 mm
Maximum slew rate	180 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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CY28373

Universal Single Chip Clock Solution for SiS658 Pentium

Features

• Supports SiS658 Pentium

4 chipsets

• Supports Pentium 4 processor

• Provides:

— 4 Differential programmable CPU clock pairs

— 2 MREF clocks for DMCG

— 2 ZCLK for MuTIOL

— 2 Low-skew/jitter AGP clocks

•

— 8 Low-skew/jitter PCI clocks

— 2 Low-skew/jitter fixed PCI clocks

— 1 48M output for USB

— 1 Programmable 24M or 48M for SIO

— 2 REF 14.318 MHz

Dial-a-Frequency

and Dial-a-dB

features

Spread spectrum for best EMI reduction

SMBus compatible for programmability

56-pin SSOP package

Block Diagram

Pin Configuration

[1]

VSSREF

*MULSEL/REF0

**FS2/REF1

VDDREF

XIN

XOUT

VSSPCI

**FS4/PCI_F0

**FS3/PCI_F1

VDDPCI

VSSPCI

PCI0

PCI1

PCI2

VDDPCI

VSSPCI

PCI3

PCI4

PCI5

VDDPCI

PCI6/*PCI_STP#

PCI7/*CPU_STP#

SDATA

VSS48

**FS0/48M

**FS1/24_48M

VDD48

*VTT_PWRGD/*PD#

VDDMREF

MREF

MREF_B

VSSMREF

SCLK

CPUT3

CPUC3

VDDCPU

CPUT2

CPUC2

VSSCPU

CPUT1

CPUC1

VDDCPU

CPUT0

CPUC0

VSSCPU

IREF

VDDA

VSSA

VDDAGP

AGP1

AGP0

VSSAGP

VDDZ

ZCLK1

ZCLK0/*MODE

VSSZ

XIN

XOUT

PLL1

CPU_STP#

IREF

FS(0:4)

MULSEL

VTTPWRGD

PCI_STP#

PLL2

Power

Latch

REF(0:1)

CPUT(0:3)

CPUC(0:3)

MREF/

MREFB

AGP(0:1)

ZCLK(0:1)

PCI(0:7)

PCI_F(0:1)

48M

48M_24M

PD#

SDATA

SCLK

PwrDn

Logic

I2C

Logic

Note:

1. Pins marked with [*] have 200-KΩ internal pull-up resistors. Pins marked with [**] have 200-KΩ internal pull-down resistors

Cypress Semiconductor Corporation

Document #: 38-07460 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134 • 408-943-2600

Revised December 18, 2002

CY28373

CY28373OC Related Products

	CY28373OC	CY28373OCT
Description	Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, SSOP-56	Processor Specific Clock Generator, 200MHz, CMOS, PDSO56, SSOP-56
Is it Rohs certified?	incompatible	incompatible
Maker	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	SSOP	SSOP
package instruction	SSOP-56	SSOP-56
Contacts	56	56
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
JESD-30 code	R-PDSO-G56	R-PDSO-G56
JESD-609 code	e0	e0
length	18.415 mm	18.415 mm
Number of terminals	56	56
Maximum operating temperature	70 °C	70 °C
Maximum output clock frequency	200 MHz	200 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP
Encapsulate equivalent code	SSOP56,.4	SSOP56,.4
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V
Master clock/crystal nominal frequency	14.318 MHz	14.318 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.794 mm	2.794 mm
Maximum slew rate	180 mA	180 mA
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	7.5 mm	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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