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ISO-CMOS ST-BUS
TM
Family
MT8976
T1/ESF Framer Circuit
Data Sheet
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D3/D4 or ESF framing and SLC-96 compatible
2 frame elastic buffer with 32
µsec
jitter buffer
Insertion and detection of A, B,C,D bits.
Signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow alarm and blue alarm signal capabilities
Bipolar violation count, F
T
error count, CRC error
count
Selectable robbed bit signalling
Frame and superframe sync. signals, Tx and Rx
AMI encoding and decoding
Per channel, overall, and remote loop around
Digital phase detector between T1 line & ST-BUS
One uncommitted scan point and drive point
Pin compatible with MT8977 and MT8979
ST-BUS compatible
September 2005
Ordering Information
MT8976AP
44 Pin PLCC
Tubes
MT8976APR
44 Pin PLCC
Tape & Reel
MT8976AE
28 Pin PDIP
Tubes
MT8976APR1 44 Pin PLCC*
Tape & Reel
MT8976AP1
44 Pin PLCC*
Tubes
MT8976AE1
28 Pin PDIP*
Tubes
*Pb Free Matte Tin
-40°C to +85°C
Applications
•
•
•
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
Description
The MT8976 is Zarlink’s second generation T1
interface solution. The MT8976 meets the Extended
Super Frame format (ESF), the current D3/D4 format
and is compatible with SLC-96 systems.
The MT8976 interfaces to DS1 1.544 Mbit/sec digital
trunk.
TxSF
C2i
F0i
RxSF
DSTo
DSTi
C1.5i
ST-BUS
Timing
Circuitry
2 Frame
Elastic Buffer
with Slip
Control
DS1
Link
Interface
2048-1544
Converter
RxFDLClk
RxFDL
RxA
Remote &
Digital
Loopbacks
RxB
TxA
TxB
TxFDLClk
TxFDL
RxD
Serial
Control
Interface
ABCD
Signalling RAM
E1.5i
Phase
Detector
DS1
Counter
Data
Interface
CSTi0
CSTi1
CSTo
XCtl
XSt
Control Logic
•
E8Ko
V
SS
V
DD
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8976
VSS
DSTo
NC
TxB
TxA
VDD
IC
NC
F0i
NC
E1.5i
Data Sheet
28 PIN PDIP
Figure 2 - Pin Connections
.
Pin Description
Pin #
Name
DIP
PLCC
Description
Transmit A Output.
Unipolar output that can be used in conjunction with TxB and external
line driver circuitry to generate the bipolar DS1 signal.
Transmit B Output.
Unipolar output that can be used in conjunction with TxA and external
line driver circuitry to generate the bipolar DS1 signal.
Data ST-BUS Output.
A 2048 kbit/s serial output stream which contains the 24 PCM or
data channels received from the DS1 line.
No Connection.
Receive A Complementary Input.
Accepts a unipolar split phase signal decoded externally
from the received DS1 bipolar signal. This input, in conjunction with RxB, detects bipolar
violations in the received signal.
Receive B Complementary Input.
Accepts a unipolar split phase signal decoded externally
from the received DS1 bipolar signal. This input, in conjunction with RxA, detects bipolar
violations in the received signal.
Receive Data Input.
Unipolar RZ data signal decoded from the received DS1 signal.
Generally the signals input at RxA and RxB are combined externally with a NAND gate and
the resulting composite signal is input at this pin.
Control ST-BUS Input #1.
A 2048 kbit/s serial control stream which carries 24 per-channel
control words.
Transmit Facility Data Link (Input).
A 4 kHz serial input stream that is multiplexed into
the FDL position in the ESF mode, or the F
s
pattern when in SLC-96 mode. It is clocked in on
the rising edge of TxFDLClk.
1
2
3
4
5
2
3
5
4
9
TxA
TxB
DSTo
NC
RxA
6
10
RxB
7
11
RxD
8
9
13
14
CSTi1
TxFDL
2
Zarlink Semiconductor Inc.
VSS
CSTi0
E8Ko
NC
VSS
XCtl
XSt
NC
CSTo
RxFDLClk
DSTi
44 PIN PLCC
TxA
TxB
DSTo
NC
RxA
RxB
RxD
CSTi1
TxFDL
TxFDLClk
NC
CSTi0
E8Ko
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
IC
F0i
E1.5i
C1.5i
RxSF
TxSF
C2i
RxFDL
DSTi
RxFDLClk
CSTo
XSt
XCtl
NC
NC
RxA
RxB
RxD
NC
CSTi1
TxFDL
NC
TxFDLClk
NC
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
29
17
18 19 20 21 22 23 24 25 26 27 28
C1.5i
RxSF
TxSF
NC
NC
C2i
NC
NC
NC
NC
RxFDL
MT8976
Pin Description (continued)
Pin #
Name
DIP
PLCC
Data Sheet
Description
Transmit Facility Data Link Clock (Output).
A 4 kHz clock used to clock in the FDL data.
No connection.
Control ST-BUS Input #0.
A 2048 kbit/s serial control stream that contains 24 per channel
control words and two master control words.
Extracted 8 kHz Output.
The E1.5i clock is internally divided by 193 to produce an 8 kHz
clock which is aligned with the received DS1 frame and output at this pin. The 8 kHz signal
is derived from C1.5 in Digital Loopback mode.
System Ground.
External Control (Output).
This is an uncommitted external output pin which is set or reset
via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated once per frame.
External Status (Schmitt Trigger Input).
The state of this pin is sampled once per frame
and the status is reported in bit 5 of Master Status Word 2 on CSTo.
Control ST-BUS Output.
This is a 2048 kbit/s serial control stream which provides the 24
per-channel status words, and two master status words.
Receive Facility Data Link Clock (Output).
A 4 kHz clock signal used to clock out FDL
information. The data is clocked out on the rising edge of RxFDLClk.
Data ST-BUS Input.
This pin accepts a 2048 kbit/s serial stream which contains the 24
PCM or data channels to be transmitted on the T1 trunk.
Received Facility Data Link (Output).
A 4 kHz serial output stream that is demultiplexed
from the FDL in ESF mode, or the received F
S
bit pattern in SLC-96 mode. It is clocked out
on the rising edge of RxFDLClk.
2.048 MHz Clock Input.
This is the master clock used for clocking serial data into DSTi,
CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.
Transmit Superframe Pulse Input.
A low going pulse applied at this pin will make the next
transmit frame the first frame of a superframe. The device will free run if this pin is held
high.
Received Superframe Pulse Output.
A pulse output on this pin designates that the next
frame of data on the ST-BUS is from frame 1 of the received superframe. The period is 12
frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are output only when the
device is synchronized to the received DS1 signal.
1.544 MHz Clock Input.
This is the DS1 transmit clock and is used to output data on TxA
and TxB. It must be phase-locked to C2i. Data is clocked out on the rising edge of C1.5i.
1.544 MHz Extracted Clock (Input).
This clock which is extracted from the received data
is used to clock in data at RxA, RxB and RxD . The falling edge of the clock is nominally
aligned with the center of the received bit on RxD, RxA and RxB.
Frame Pulse Input.
This is the frame synchronization signal which defines the beginning of
the 32 channel ST-BUS frame.
10
11
12
13
16
TxFDLClk
NC
19
20
CSTi0
E8Ko
14
15
16
17
18
19
20
6, 18,
22
23
24
26
27
28
29
V
SS
XCtl
XSt
CSTo
RxFDLClk
DSTi
RxFDL
21
22
34
37
C2i
TxSF
23
38
RxSF
24
25
39
40
C1.5i
E1.5i
26
42
F0i
3
Zarlink Semiconductor Inc.
MT8976
Pin Description (continued)
Pin #
Name
DIP
PLCC
Data Sheet
Description
Internal Connection.
Tied to V
SS
for normal operation.
Positive Power Supply Input.
+5V
±
5%.
27
28
44
1
IC
V
DD
4
Zarlink Semiconductor Inc.
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