M58LW064A
M58LW064B
64 Mbit (x16 and x16/x32, Block Erase)
Low Voltage Flash Memories
PRODUCT PREVIEW
s
s
s
M58LW064A x16 organisation,
M58LW064B x16/x32 selectable
MULTI-BIT CELL for HIGH DENSITY and LOW
COST
SUPPLY VOLTAGE
– V
DD
= 2.7V to 3.6V Supply Voltage
– V
DDQ
= 2.7V to 3.6V or 1.8V to 2.5V
Input/Output Supply Voltage
TSOP56 (NF)
1
86
s
TSOP86 II (NH)
s
PIPELINED SYNCHRONOUS BURST
INTERFACE
SYNCHRONOUS/ASYNCHRONOUS READ
– Synchronous Burst read
– Asynchronous Random and Latch Enabled
Controlled Read, with Page Read
PQFP80 (T)
LBGA54 (ZA)
FBGA
s
s
ACCESS TIME
– Synchronous Burst Read up to 66MHz
– Asynchronous Page Mode Read 150/25ns,
Random Read 150ns
Figure 1. Logic Diagram
VDD VDDQ
22
A1-A22
VPP
W
E
G
RP
L
B
K
WORD
(1)
s
PROGRAMMING TIME
– 16 Word or 8 Double-Word Write Buffer
– 12us Word effective programming time
32
DQ0-DQ31
s
MEMORY BLOCKS
– 64 Equal blocks of 1 Mbit
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code M58LW064A: 17h
– Device Code M58LW064B: 14h
s
RB
M58LW064A
M58LW064B
R
DESCRIPTION
The M58LW064 is a non-volatile Flash memory
that may be erased electrically at the block level
and programmed in-system on a 16 Word or 8
Double-Word basis using a 2.7V to 3.6V supply for
the circuit and a supply down to 1.8V for the Input
and Output buffers. The M58LW064A is organised
as 4M by 16 bit. The M58LW064B has 4M by 16
bit or 2M by 32 bit organisation selectable by the
Word Organisation WORD input. Both devices are
internally configured as 64 blocks of 1 Mbit each.
VSS
AI03223
Note: 1. Only on M58LW064B.
May 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/53
M58LW064A, M58LW064B
Table 1. Signal Names
A1-A22
A2-A22
Address Inputs x16 Organisation
Address inputs x32 Organisation
Data Input/Output x16 and x32
Organisation Command Input,
Electronic Signature Output, Block
Protection Ststus Output, Status
Register Output
Data Input/Output x16 and x32
Organisation
Data Input/Output x32 Organisation
Burst Address Advance
Chip Enable
Output Enable
Burst Clock
Latch Enable
Valid Data Ready (open drain output)
Ready/Busy (open drain output)
Reset/Power-down
Program/Erase Enable
Write Enable
Word Organisation (M58LW064B only)
Supply Voltage
Input/Output Supply Voltage
Ground
No internal connection
Don’t Use (internally connected)
DQ0-DQ7
DQ8-DQ15
DQ16-DQ31
B
E
G
K
L
R
RB
RP
V
PP
W
WORD
V
DD
V
DDQ
V
SS
NC
DU
The devices support Asynchronous Random and
Latch Enable Controlled Read with Page mode as
well as Synchronous Burst Read with a config-
urable burst. They also support pipelined synchro-
nous Burst Read. Writing is Asynchronous or
Asynchronous Latch Enable Controlled.
The configurable synchronous burst read interface
allows a high data transfer rate controlled by the
Burst Clock K signal. It is capable of bursting fixed
or unlimited lengths of data. The burst type, laten-
cy and length are configurable and can be easily
adapted to a large variety of system clock frequen-
cies and microprocessors. A 16 Word or 8 Double-
Word Write Buffer improves effective program-
ming speed by up to 20 times when data is pro-
grammed in full buffer increments. Effective Word
programming takes typically 12µs. The array ma-
trix organisation allows each block to be erased
and reprogrammed without affecting other blocks.
Program and Erase operations can be suspended
in order to perform either Read or Program in any
other block and then resumed. All blocks are pro-
tected against spurious programming and erase
cycles at power-up. Any block can be separately
protected at any time. The block protection bits
can also be deleted, this is executed as one se-
quence for all blocks simultaneously. Block protec-
tion can be temporarily disabled. Each block can
be programmed and erased over 100,000 cycles.
Block erase is performed in typically 1 second.
An internal Command Interface (C.I.) decodes In-
structions to access/modify the memory content.
The Program/Erase Controller (P/E.C.) automati-
cally executes the algorithms taking care of the
timings required by the program and erase opera-
tions. Verification is internally performed and a
Status Register tracks the status of the operations.
The Ready/Busy output RB indicates the comple-
tion of operations.
Instructions are written to the memory through the
Command Interface (C.I.) using standard micro-
processor write timings. The device supports the
Common Flash Interface (CFI) command set defi-
nition.
A Reset/Power-down mode is entered when the
RP input is Low. In this mode the power consump-
tion is lower than in the normal standby mode, the
device is write protected and both the Status and
the Burst Configuration Registers are cleared. A
recovery time is required when the RP input goes
High.
The device is offered in various package versions,
TSOP56 (14 x 20 mm), TSOP86 Type II (11.76 x
22.22 mm) and LBGA54 1mm ball pitch for the
M58LW064A and PQFP80 for the M58LW064B.
2/53
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
