IBM041816CBLBC-27 datasheet, PDF

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IBM041816CBLBC-27: DescriptionDDR SRAM, 1MX18, 2ns, CMOS, PBGA153, BGA-153; Categorystorage storage; File Size314KB，25 Pages; ManufacturerIBM; Websitehttp://www.ibm.com

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IBM041816CBLBC-27 Overview

DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, BGA-153

IBM041816CBLBC-27 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IBM
Parts packaging code	BGA
package instruction	BGA, BGA153,9X17,50
Contacts	153
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	2 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	370 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B153
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	153
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA153,9X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
power supply	1.8,2.5 V
Certification status	Not Qualified
Maximum seat height	2.679 mm
Maximum standby current	0.2 A
Minimum standby current	2.38 V
Maximum slew rate	0.515 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

Features

• 512K x 36 or 1M x 18 organization

• CMOS technology

• Double-data-rate and single-data-rate synchro-

nous mode of operation

• Pipeline mode of operation

• Self-timed late write with full data coherency

• Single differential clock

• 1.8V high-speed transceiver logic (HSTL) I/O

•

2.5V power supply, 1.8V V

DDQ

• Registered addresses, controls, and data-ins

• Burst mode of operation

• Common I/O

• Asynchronous output enable

• Boundary scan using a limited set of JTAG

1149.1 functions

• 9 x 17 bump ball grid array package with SRAM

JEDEC standard pinout and boundary SCAN

order

• Programmable impedance output driver

Description

The IBM043616CBLBC and IBM041816CBLBC

16Mb SRAMs are synchronous pipeline-mode, high-

performance CMOS static random-access memo-

ries that have wide I/O and achieve 2.2ns cycle

times. Single differential CK clocks are used to ini-

tialize the read/write operation, and all internal oper-

ations are self-timed. At the rising edge of the CK

clock, addresses and controls are registered inter-

nally. Data-outs are updated from output registers

on the next rising and falling edges of the CK clock,

hence the double data rate. Internal write buffers

allow write data to follow one cycle after addresses

and controls. The SRAM is operated with a single

2.5V power supply and is compatible with HSTL I/O

interfaces.

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June 3, 2002

Page 1 of 25

IBM043616CBLBC

IBM041816CBLBC

16Mb (512K x 36 & 1M x 18) SRAM

SRAM Features

Double Data Rate (DDR) and Single Data Rate (SDR) Modes

The timing diagram on page 6 shows input and output data placements for both DDR and SDR modes. In

DDR read mode, two sets of data-outs are generated from the second rising and falling edges of the CK

clock, assuming the first rising edge of the CK clock samples the base address. The first of the two data-out

sets (DOUT-A) is generated from the sampled base address (Base-A). The second data-out set (DOUT-A’) is

generated from the next burst-order address, according to the burst-order definition. Similarly, a DDR write

requires data-in placement on the second rising and falling CK edges. In SDR read mode, only one set of

data-outs is generated from the second rising CK edge. In SDR write mode, one set of data-ins is sampled on

the second rising CK edge. The user may switch from DDR to SDR mode (or vice-versa) during any LOAD

(B1 = 0) operation.

Late Write

The late-write function allows write data to be registered one cycle after addresses and controls. This feature

eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.

Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the

third write cycle. Read-cycle addresses are monitored to determine if read data is to be supplied from the

SRAM array or the write buffer. Full data coherency is maintained for both DDR and SDR operations. As a

result, NOP (write buffer flush) operations are not required going from write cycles to read cycles.

Echo Clocks

Echo clocks CQ and CQ are generated from rising and falling edges of the CK clock, with access times repre-

sentative of the data-outs. Echo clocks keep running during write and NOP operations. Echo-clock operation

is identical for both double-data-rate and single-data-rate operations. The close tracking of echo clocks and

data-out timings allows the echo clocks to be used as capture clocks for the data-outs by the receiving

device.

CBLBCds.fm.00

June 3, 2002

Page 5 of 25

IBM041816CBLBC-27 Related Products

	IBM041816CBLBC-27	IBM041816CBLBC-30	IBM041816CBLBC-24	IBM041816CBLBC-22
Description	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, BGA-153	DDR SRAM, 1MX18, 1.7ns, CMOS, PBGA153, BGA-153	DDR SRAM, 1MX18, 2.1ns, CMOS, PBGA153, BGA-153	DDR SRAM, 1MX18, 2.1ns, CMOS, PBGA153, BGA-153
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	BGA, BGA153,9X17,50	BGA, BGA153,9X17,50	BGA, BGA153,9X17,50	BGA, BGA153,9X17,50
Contacts	153	153	153	153
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	2 ns	1.7 ns	2.1 ns	2.1 ns
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	370 MHz	333 MHz	417 MHz	455 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-PBGA-B153	R-PBGA-B153	R-PBGA-B153	R-PBGA-B153
JESD-609 code	e0	e0	e0	e0
length	22 mm	22 mm	22 mm	22 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	18	18	18
Number of functions	1	1	1	1
Number of terminals	153	153	153	153
word count	1048576 words	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
organize	1MX18	1MX18	1MX18	1MX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA
Encapsulate equivalent code	BGA153,9X17,50	BGA153,9X17,50	BGA153,9X17,50	BGA153,9X17,50
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
power supply	1.8,2.5 V	1.8,2.5 V	1.8,2.5 V	1.8,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.679 mm	2.679 mm	2.679 mm	2.679 mm
Maximum standby current	0.2 A	0.2 A	0.2 A	0.2 A
Minimum standby current	2.38 V	2.38 V	2.38 V	2.38 V
Maximum slew rate	0.515 mA	0.47 mA	0.54 mA	0.625 mA
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm	14 mm
Maker	IBM	-	IBM	IBM

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