Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
SOT23-5
PACKAGE CODE
Outline Number
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
Thermal Resistance, Multi-Layer Board:
Junction to Ambient (θ
JA
)
Junction to Case (θ
JC
)
255.9°C/W
81°C/W
324.3°C/W
82°C/W
21-0057
90-0174
U5+2/U5+2A
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages.
Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
www.maximintegrated.com
Maxim Integrated │
2
MAX6316–MAX6322
5-Pin μP Supervisory Circuits with
Watchdog and Manual Reset
Electrical Characteristics
PARAMETER
Operating Voltage Range
Supply Current
(V
CC
= 2.5V to 5.5V, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are at T
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;ENTITY control ISPORT( clk,rest:IN STD_LOGIC;wradd,rdadd:in std_logic_vector (12 downto 0);wr,rd:OUT STD_LOGIC);
END control;ARCHITECTURE behav OF control ISv...
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FPGA/CPLD
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