QL7180 DSP Data Sheet
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Combining Embedded DSP Blocks, Performance, Density
and Embedded RAM
1.0 Device Highlights
Clock Network
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9 global clock networks
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1 dedicated, 8 programmable
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16 I/O (high drive) networks:
High Speed Customizable Logic
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0.25u, 5 layer metal CMOS process
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2.5 V Vcc, 2.5 / 3.3 V drive capable I/O
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512 programmable I/O
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4,032 Logic Cells
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660,000 max system gates
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Muxed based architecture,
2 banks per I/O
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20 Quad-net networks: 5 per quadrant
Programmable I/O
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High performance enhanced I/O:
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less than 3 ns Tco
Programmable slew rate control
Programmable I/O standards
LVTTL, LVCMOS, PCI, GTL+, SSTL2,
and SSTL3
8 independent I/O banks
3 register configuration: Input, Output, OE
non-volatile technology
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Completely customizable for any
digital applications
Dual Port SRAM
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36 blocks of dual-port SRAM
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2,304 bit dual port high performance
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Parameterized IP
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Free parameterized IP administered with a
DSP Wizard
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Supports multiple and hierarchical IP
instantiations
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SRAM Blocks
Total of 82,900 bits
RAM / ROM / FIFO Wizard for automatic
configuration
Configurable and cascadable
Array sizes of 2, 4, 9, and 18
< 3 ns access times, 300+ MHz FIFO
Applications
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Signal processing operators
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Signal processing functions
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Networking / communications for VoIP
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Speech / voice processing
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Channel coding
Figure 1: Embedded QuickDSP Block Diagram
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QL7180 QuickDSP
TM
Data Sheet Rev B
1
QL7180 DSP Data Sheet
2.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=1.00)
The AC Specifications, Logic Cell diagrams and waveforms are provided below.
Figure 2: QuickDSP Logic Cell
Table 1: Logic Cells
Symbol
Logic Cells
tPD
tSU
thl
tCLK
tCWHI
tCWLO
tSET
tRESET
tSW
tRW
Combinatorial delay: time taken by the combinatorial circuit to output
Setup time: the amount of time the synchronous input of the flip flop must be stable before
the active clock edge
Hold time: the amount of time the synchronous input of the flip flop must be stable after the
active block edge
Clock to out delay: the amount of time the synchronous input of the flip flop must be stable
after the active block edge
Clock High Time: the length of time that the clock stays high
Clock Low Time: the length of time that the clock stays low
Set Delay: amount of time between when the flip flop is ”set” (high)
and when Q is consequent “set” (high)
Reset Delay: amount of time between when the flip flop is ”reset” (low) and when Q is
consequent “reset” (low)
Set Width: length of time that the SET signal remains high
(low if active low)
Reset Width: length of time that the RESET signal remains high
(low if active low)
Parameter
Propagation
delay (ns)
1
0.257
0.22
0
0.255
0.46
0.46
0.18
0.09
0.3
0.3
2
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www.quicklogic.com
© 2001 QuickLogic Corporation
QL7180 DSP Data Sheet
Figure 3: Logic Cell Flip Flop
Figure 4: Logic Cell Flip Flop Timings - First Waveform
Figure 5: Logic Cell Flip Flop Timings - Second Waveform
QL7180 QuickDSP
TM
Data Sheet Rev B
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QL7180 DSP Data Sheet
Figure 6: QuickDSP Global Clock Structure
Table 2: QuickDSP Clock Performance
Clock Performance
Global
Macro
I/O
Skew
1.51 ns
2.06 ns
0.55 ns
Dedicated
1.59 ns
1.73 ns
0.14 ns
Table 3: QuickDSP Input Register Cell
Symbol
Input Register Cell Only
tGCKP
GCKB
Global clock pin delay
Global clock buffer delay
Parameter
Propagation delay (ns)
Figure 7: Global Clock Structure Schematic
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www.quicklogic.com
© 2001 QuickLogic Corporation
QL7180 DSP Data Sheet
Figure 8: QuickRAM Module
Table 4: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation
delay (ns)
1
0.675
0
0.654
0
0.623
0
4.38
RAM Cell Synchronous Write Timing
TSWA
THWA
TSWD
THWD
TSWE
THWE
TWCRD
WA Setup Time to WCLK: the amount of time the WRITE ADDRESS
must be stable before the active edge of the WRITE CLOCK
WA Hold Time to WCLK: the amount of time the WRITE ADDRESS must
be stable after the active edge of the WRITE CLOCK
WD Setup Time to WCLK: the amount of time the WRITE DATA must be
stable before the active edge of the WRITE CLOCK
WD Hold Time to WCLK: the amount of time the WRITE DATA must be
stable after the active edge of the WRITE CLOCK
WE Setup Time to WCLK: the amount of time the WRITE ENABLE must
be stable before the active edge of the WRITE CLOCK
WE Hold Time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
WCLK to RD (WA=RA) [5]: the amount of time between the active
WRITE CLOCK edge and the time when the data is available at RD
QL7180 QuickDSP
TM
Data Sheet Rev B
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