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GS8170LW72C-200IT

Description
Standard SRAM, 256KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209
Categorystorage    storage   
File Size884KB,27 Pages
ManufacturerGSI Technology
Websitehttp://www.gsitechnology.com/
Download Datasheet Parametric View All

GS8170LW72C-200IT Overview

Standard SRAM, 256KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209

GS8170LW72C-200IT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerGSI Technology
Parts packaging codeBGA
package instructionLBGA,
Contacts209
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time2.25 ns
Other featuresPIPELINED ARCHITECTURE
JESD-30 codeR-PBGA-B209
length22 mm
memory density18874368 bit
Memory IC TypeSTANDARD SRAM
memory width72
Humidity sensitivity level3
Number of functions1
Number of terminals209
word count262144 words
character code256000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize256KX72
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.7 mm
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
GS8170LW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Features
• Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAM
pinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
18Mb
Σ
1x1Lp CMOS I/O
Late Write SigmaRAM™
Functional Description
200 MHz–333 MHz
1.8 V V
DD
1.8 V I/O
SigmaRAM Family Overview
GS8170LW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
Σ
RAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
Σ
RAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The
Σ
RAM
family standard
allows a user to implement the interface protocol best suited to
the task at hand.
Σ
RAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Cycle Time
Access Time
Symbol
tKHKH
tKHQV
- 333
3.0 ns
1.6 ns
Rev: 2.03 1/2005
1/27
© 2002, GSI Technology, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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