DATASHEET
X28C512, X28C513
5V, Byte Alterable EEPROM
The X28C512, X28C513 are 64K x 8 EEPROM, fabricated
with Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable nonvolatile
memories, the X28C512, X28C513 are 5V only devices. The
X28C512, X28C513 feature the JEDEC approved pin out for
byte wide memories, compatible with industry standard
EPROMS.
The X28C512, X28C513 support a 128-byte page write
operation, effectively providing a 39µs/byte write cycle and
enabling the entire memory to be written in less than 2.5
seconds. The X28C512, X28C513 also feature DATA Polling
and Toggle Bit Polling, system software support schemes
used to indicate the early completion of a write cycle. In
addition, the X28C512, X28C513 support the software data
protection option.
FN8106
Rev 2.00
June 7, 2006
Features
• Access Time: 90ns
• Simple Byte and Page Write
- Single 5V supply
• No external high voltages or V
PP
control circuits
- Self-timed
• No erase before write
• No complex programming algorithms
• No overerase problem
• Low Power CMOS
- Active: 50mA
- Standby: 500µA
• Software Data Protection
- Protects data against system level inadvertent writes
• High Speed Page Write Capability
• Highly Reliable Direct Write
™
Cell
- Endurance: 100,000 write cycles
- Data retention: 100 years
- Early end of write detection
- DATA polling
- Toggle bit polling
• Two PLCC and LCC Pinouts
- X28C512
• X28C010 EPROM pin compatible
- X28C513
• Compatible with lower density EEPROMs
• Pb-Free Plus Anneal Available (RoHS Compliant)
FN8106 Rev 2.00
June 7, 2006
Page 1 of 21
X28C512, X28C513
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in a
high impedance state when either OE or CE is HIGH.
DATA Polling (I/O
7
)
The X28C512, X28C513 feature DATA polling as a method to
indicate to the host system that the byte write or page write
cycle has completed. DATA Polling allows a simple bit test
operation to determine the status of the X28C512, X28C513,
eliminating additional interrupt inputs or external hardware.
During the internal programming cycle, any attempt to read the
last byte written will produce the complement of that data on
I/O
7
(i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once
the programming cycle is complete, I/O
7
will reflect true data.
Write
Write operations are initiated when both CE and WE are LOW
and OE is HIGH. The X28C512, X28C513 support both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs last.
Similarly, the data is latched internally by the rising edge of
either CE or WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to completion,
typically within 5ms.
Toggle Bit (I/O
6
)
The X28C512, X28C513 also provide another method for
determining when the internal write cycle is complete. During
the internal programming cycle, I/O
6
will toggle from HIGH to
LOW and LOW to HIGH on subsequent attempts to read the
device. When the internal cycle is complete, the toggling will
cease, and the device will be accessible for additional read or
write operations.
Page Write Operation
The page write feature of the X28C512, X28C513 allows the
entire memory to be written in 2.5 seconds. Page write allows
two to one hundred twenty-eight bytes of data to be
consecutively written to the X28C512, X28C513, prior to the
commencement of the internal programming cycle. The host
can fetch data from another device within the system during a
page write operation (change the source address), but the
page address (A
7
through A
15
) for each subsequent valid write
cycle to the part during this operation must be the same as the
initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to one hundred twenty-seven bytes in
the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of the
preceding WE. If a subsequent WE HIGH to LOW transition is
not detected within 100µs, the internal automatic programming
cycle will commence. There is no page write window limitation.
Effectively, the page write window is infinitely wide, so long as
the host continues to access the device within the byte load
cycle time of 100µs.
Write Operation Status Bits
The X28C512, X28C513 provide the user two write operation
status bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown in
Figure 1.
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
FIGURE 1. STATUS BIT ASSIGNMENT
FN8106 Rev 2.00
June 7, 2006
Page 5 of 21
Embedded System
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