a
FEATURES
4-Quadrant Multiplication
Low Cost 8-Lead Package
Complete—No External Components Required
Laser-Trimmed Accuracy and Stability
Total Error within 2% of FS
Differential High Impedance X and Y Inputs
High Impedance Unity-Gain Summing Input
Laser-Trimmed 10 V Scaling Reference
APPLICATIONS
Multiplication, Division, Squaring
Modulation/Demodulation, Phase Detection
Voltage Controlled Amplifiers/Attenuators/Filters
X1
1
1
X2
2
1
10V
Low Cost
Analog Multiplier
AD633
CONNECTION DIAGRAMS
8-Lead Plastic DIP (N) Package
8
+V
S
A
7
W
Y1
3
6
Z
Y2
4
1
5
–V
S
AD633JN/AD633AN
8-Lead Plastic SOIC (RN-8) Package
PRODUCT DESCRIPTION
Y1
1
The AD633 is a functionally complete, four-quadrant, analog
multiplier. It includes high impedance, differential X and Y
inputs and a high impedance summing input (Z). The low
impedance output voltage is a nominal 10 V full scale provided
by a buried Zener. The AD633 is the first product to offer these
features in modestly priced 8-lead plastic DIP and SOIC packages.
The AD633 is laser calibrated to a guaranteed total accuracy of
2% of full scale. Nonlinearity for the Y input is typically less
than 0.1% and noise referred to the output is typically less than
100
µV
rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz band-
width, 20 V/µs slew rate, and the ability to drive capacitive loads
make the AD633 useful in a wide variety of applications where
simplicity and cost are key concerns.
The AD633’s versatility is not compromised by its simplicity.
The Z-input provides access to the output buffer amplifier,
enabling the user to sum the outputs of two or more multipliers,
increase the multiplier gain, convert the output voltage to a
current, and configure a variety of applications.
The AD633 is available in an 8-lead plastic DIP package (N)
and 8-lead SOIC (R). It is specified to operate over the 0°C to
70°C commercial temperature range (J Grade) or the –40°C to
+85°C industrial temperature range (A Grade).
1
1
10V
A
1
8
X2
Y2
2
7
X1
–V
S
3
6
+V
S
Z
4
5
W
AD633JR/AD633AR
W=
(X
1
– X
2
) (Y
1
– Y
2
)
10V
+Z
PRODUCT HIGHLIGHTS
1. The AD633 is a complete four-quadrant multiplier offered in
low cost 8-lead plastic packages. The result is a product that
is cost effective and easy to apply.
2. No external components or expensive user calibration are
required to apply the AD633.
3. Monolithic construction and laser calibration make the
device stable and reliable.
4. High (10 MΩ) input resistances make signal source loading
negligible.
5. Power supply voltages can range from
±
8 V to
±
18 V. The
internal scaling voltage is generated by a stable Zener diode;
multiplier accuracy is essentially supply insensitive.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD633–SPECIFICATIONS
(T = 25 C, V =
A
S
15 V, R
L
≥
2 k )
AD633J, AD633A
W
=
Model
TRANSFER FUNCTION
Parameter
MULTIPLIER PERFORMANCE
Total Error
T
MIN
to T
MAX
Scale Voltage Error
Supply Rejection
Nonlinearity, X
Nonlinearity, Y
X Feedthrough
Y Feedthrough
Output Offset Voltage
DYNAMICS
Small Signal BW
Slew Rate
Settling Time to 1%
OUTPUT NOISE
Spectral Density
Wideband Noise
OUTPUT
Output Voltage Swing
Short Circuit Current
INPUT AMPLIFIERS
Signal Voltage Range
Offset Voltage X, Y
CMRR X, Y
Bias Current X, Y, Z
Differential Resistance
POWER SUPPLY
Supply Voltage
Rated Performance
Operating Range
Supply Current
Conditions
–10 V
≤
X, Y
≤
+10 V
SF = 10.00 V Nominal
V
S
=
±
14 V to
±
16 V
X =
±
10 V, Y = +10 V
Y =
±
10 V, X = +10 V
Y Nulled, X =
±
10 V
X Nulled, Y =
±
10 V
(
X
1
−
X
2
Y
1
−
Y
2
10
V
)
(
)
+
Z
Max
2
Unit
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
% Full Scale
mV
MHz
V/µs
µs
µV/√Hz
mV rms
µV
rms
V
mA
V
V
mV
dB
µA
MΩ
Min
Typ
±
1
±
3
±
0.25%
±
0.01
±
0.4
±
0.1
±
0.3
±
0.1
±
5
1
20
2
0.8
1
90
1
0.4
1
0.4
50
V
O
= 0.1 V rms
V
O
= 20 V p-p
∆
V
O
= 20 V
f = 10 Hz to 5 MHz
f = 10 Hz to 10 kHz
11
R
L
= 0
Ω
Differential
Common Mode
V
CM
=
±
10 V, f = 50 Hz
30
10
10
60
40
±
5
80
0.8
10
30
2.0
±
15
8
Quiescent
4
6
18
V
V
mA
Specifications shown in
boldface
are tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in
boldface
are tested on all production units.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package
Description
Plastic DIP
Plastic SOIC
13" Tape and Reel
7" Tape and Reel
Plastic DIP
Plastic SOIC
13" Tape and Reel
7" Tape and Reel
Package
Option
N-8
RN-8
RN-8
RN-8
N-8
RN-8
RN-8
RN-8
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . 500 mW
Input Voltages
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
18 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
AD633J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
AD633A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational section of this
specification is not implied.
2
8-Lead Plastic DIP Package:
θ
JA
= 90°C/W; 8-Lead Small Outline Package:
θ
JA
=
155°C/W.
3
For supply voltages less than
±18
V, the absolute maximum input voltage is equal to
the supply voltage.
Model
AD633AN
AD633AR
AD633AR-REEL
AD633AR-REEL7
AD633JN
AD633JR
AD633JR-REEL
AD633JR-REEL7
–2–
REV. E
Typical Performance Characteristics– AD633
100
0dB = 0.1V rms, R
L
= 2k
0
C
L
= 1000pF
OUTPUT RESPONSE – dB
90
80
70
60
50
40
30
TYPICAL
FOR X,Y
INPUTS
–10
–20
NORMAL
CONNECTION
CMRR – dB
C
L
= 0dB
–30
10k
1M
100k
FREQUENCY – Hz
10M
20
100
1k
10k
FREQUENCY – Hz
100k
1M
TPC 1. Frequency Response
TPC 4. CMRR vs. Frequency
700
1.5
V/
Hz
NOISE SPECTRAL DENSITY –
600
BIAS CURRENT – nA
1
500
400
0.5
300
200
–60
–40
–20
0
20
40
60
80
100
120
140
0
10
100
TEMPERATURE – C
1k
FREQUENCY – Hz
10k
100k
TPC 2. Input Bias Current vs. Temperature (X, Y, or
Z Inputs)
TPC 5. Noise Spectral Density vs. Frequency
14
PEAK POSITIVE OR NEGATIVE SIGNAL – V
1000
12
OUTPUT, R
L
10
ALL INPUTS
8
2k
P-P FEEDTHROUGH – mV
100
Y-FEEDTHROUGH
X-FEEDTHROUGH
10
1
6
4
0
8
10
12
14
16
18
PEAK POSITIVE OR NEGATIVE SUPPLY – V
20
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
TPC 3. Input and Output Signal Ranges vs. Supply
Voltages
TPC 6. AC Feedthrough vs. Frequency
REV. E
–3–
AD633
FUNCTIONAL DESCRIPTION
APPLICATIONS
The AD633 is a low cost multiplier comprising a translinear
core, a buried Zener reference, and a unity gain connected
output amplifier with an accessible summing node. Figure 1
shows the functional block diagram. The differential X and Y
inputs are converted to differential currents by voltage-to-current
converters. The product of these currents is generated by the
multiplying core. A buried Zener reference provides an overall
scale factor of 10 V. The sum of (X
×
Y)/10 + Z is then applied
to the output amplifier. The amplifier summing node Z allows
the user to add two or more multiplier outputs, convert the
output voltage to a current, and configure various analog com-
putational functions.
+V
S
The AD633 is well suited for such applications as modulation
and demodulation, automatic gain control, power measurement,
voltage controlled amplifiers, and frequency doublers. Note that
these applications show the pin connections for the AD633JN
pinout (8-lead DIP), which differs from the AD633JR pinout
(8-lead SOIC).
Multiplier Connections
Figure 3 shows the basic connections for multiplication. The X
and Y inputs will normally have their negative nodes grounded,
but they are fully differential, and in many applications the
grounded inputs may be reversed (to facilitate interfacing with
signals of a particular polarity while achieving some desired
output polarity) or both may be driven.
+15V
0.1 F
X
INPUT
1
2
3
4
X1
1
1
A
1
10V
8
X2
2
7
W
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
0.1 F
–15V
10V
OPTIONAL SUMMING
INPUT, Z
W=
(X
1
– X
2
) (Y
1
– Y
2
)
+Z
Y1
3
6
Z
Y
INPUT
AD633JN
Y2
4
1
AD633
5
–V
S
Figure 1. Functional Block Diagram (AD633JN
Pinout Shown)
Figure 3. Basic Multiplier Connections
Squaring and Frequency Doubling
Inspection of the block diagram shows the overall transfer func-
tion to be:
W
=
(
X
1
−
X
2
Y
1
−
Y
2
10
V
)
(
)
+
Z
(1)
As Figure 4 shows, squaring of an input signal, E, is achieved
simply by connecting the X and Y inputs in parallel to produce
an output of E
2
/10 V. The input may have either polarity, but
the output will be positive. However, the output polarity may be
reversed by interchanging the X or Y inputs. The Z input may
be used to add a further signal to the output.
+15V
0.1 F
E
1
2
3
4
ERROR SOURCES
Multiplier errors consist primarily of input and output offsets,
scale factor error, and nonlinearity in the multiplying core. The
input and output offsets can be eliminated by using the optional
trim of Figure 2. This scheme reduces the net error to scale factor
errors (gain error) and an irreducible nonlinearity component in
the multiplying core. The X and Y nonlinearities are typically
0.4% and 0.1% of full scale, respectively. Scale factor error is
typically 0.25% of full scale. The high impedance Z input should
always be referenced to the ground point of the driven system,
particularly if this is remote. Likewise, the differential X and Y
inputs should be referenced to their respective grounds to realize
the full accuracy of the AD633.
+V
S
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
0.1 F
–15V
W=
E
2
10V
AD633JN
Figure 4. Connections for Squaring
When the input is a sine wave
E
sin
ωt,
this squarer behaves as a
frequency doubler, since
50k
300k
1k
50mV
TO APPROPRIATE
INPUT TERMINAL
(e.g., X
2
, X
2
, Z)
(
E
sin
ω
t
)
10
V
2
=
E
2
1
−
cos 2
ω
t
20
V
(
)
(2)
–V
S
Figure 2. Optional Offset Trim Configuration
Equation 2 shows a dc term at the output that will vary strongly
with the amplitude of the input,
E.
This can be avoided using
the connections shown in Figure 5, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity:
cos
θ
sin
θ =
1
sin 2
θ
2
(
)
(3)
–4–
REV. E
AD633
+15V
0.1 F
E
R
1
2
3
4
R
10k
+15V
W=
R2
3k
E
2
10V
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
0.1 F
–15V
+15V
0.1 F
R
10k
E
0.1 F
E
X
1
2
AD633JN
C
R1
1k
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
–15V
W' = –10V
E
E
X
AD633JN
AD711
0.1 F
–15V
3
4
0.1 F
Figure 5. ”Bounceless” Frequency Doubler
At
ω
o
= 1/CR, the X input leads the input signal by 45° (and is
attenuated by
√2),
and the Y input lags the X input by 45° (and
is also attenuated by
√2).
Since the X and Y inputs are 90° out of
phase, the response of the circuit will be (satisfying Equation 3):
Figure 7. Connections for Division
W
=
=
1
E
E
(
sin
ω
o
t
+
45
°
) (
sin
ω
o
t
−
45
°
)
(
10
V
)
2
2
E
(
sin 2
ω
o
t
)
(
40
V
)
2
Likewise, Figure 7 shows how to implement a divider using a
multiplier in a feedback loop. The transfer function for the
divider is
W
'
= −
(
10
V
)
E
E
X
+15V
0.1 F
X
INPUT
1
2
(6)
(4)
which has no dc component. Resistors R1 and R2 are included to
restore the output amplitude to 10 V for an input amplitude of 10 V.
The amplitude of the output is only a weak function of frequency:
the output amplitude will be 0.5% too low at
ω
= 0.9
ω
o
, and
ω
o
= 1.1
ω
o
.
Generating Inverse Functions
X1
X2
Y1
Y2
+V
S 8
W
7
R1
R2
Z
6
–V
S 5
0.1 F
–15V
S
W=
(X
1
– X
2
) (Y
1
– Y
2
)
10V
1k
R1, R2
(R1 + R2)
R1
100k
+S
AD633JN
Y
INPUT
3
4
Inverse functions of multiplication, such as division and square
rooting, can be implemented by placing a multiplier in the feed-
back loop of an op amp. Figure 6 shows how to implement a
square rooter with the transfer function
Figure 8. Connections for Variable Scale Factor
Variable Scale Factor
W
=
(
10
E
)
V
+15V
+15V
0.1 F
7
(5)
for the condition E < 0.
In some instances, it may be desirable to use a scaling voltage
other than 10 V. The connections shown in Figure 8 increase
the gain of the system by the ratio (R1 + R2)/R1. This ratio is
limited to 100 in practical applications. The summing input, S,
may be used to add an additional signal to the output or it may
be grounded.
Current Output
0.1 F
1
2
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
1N4148
AD633JN
3
4
OP27
E
4
0.1 F
0.1 F
The AD633’s voltage output can be converted to a current
output by the addition of a resistor R between the AD633’s W
and Z pins as shown in Figure 9. This arrangement forms
+15V
–15V
1N4148
–15V
W=
(
10E
)
V
0.1 F
X
INPUT
1
2
3
4
X1
X2
Y1
Y2
+V
S 8
W
7
Z
6
–V
S 5
0.1 F
–15V
R
I
O
=
1
R
1k
(X
1
– X
2
) (Y
1
– Y
2
)
10V
R
100k
Figure 6. Connections for Square Rooting
AD633JN
Y
INPUT
Figure 9. Current Output Connections
REV. E
–5–
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