ISL6444
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN9069
Rev 3.00
Apr 12, 2007
Dual PWM Controller with DDR Memory Option for Gateway Applications
The ISL6444 PWM controller provides high efficiency and
regulation for two output voltages adjustable in the range from
0.9V to 5.5V that are required to power I/O, chip-sets, and
memory banks in high-performance notebook computers,
PDAs, and Internet appliances.
Synchronous rectification and hysteretic operation at light
loads contribute to a high efficiency over a wide range of
loads. The hysteretic mode of operation can be disabled
separately on each PWM converter if continuous conduction
operation is desired for all load levels. Efficiency is even
further enhanced by using MOSFET’s r
DS(ON)
as a current
sense component.
Feed-forward ramp modulation, current mode control
scheme, and internal feed-back compensation provide fast
response to load transients. Out-of-phase operation with a
180
o
phase shift reduces the input current ripple.
The controller can be transformed in a complete DDR
memory power supply solution by activating a DDR pin. In
DDR mode of operation one of the channels tracks the
output voltage of another channel and provides output
current sink and source capability–features essential for
proper powering of DDR chips. The buffered reference
voltage required by this type of memory is also provided.
The ISL6444 monitors the output voltages. Each PWM
controller generates a PGOOD (power good) signal when
the soft-start is completed and the output is within ±10% of
the set point.
A built-in overvoltage protection prevents output voltage
from going above 115% of the set point. Normal operation
automatically restores when the overvoltage conditions go
away. Undervoltage protection latches the chip off when
either output drops below 75% of its set value after the
soft-start sequence for this output is completed. An
adjustable overcurrent function monitors the output current
by sensing the voltage drop across the lower MOSFET. If
precision current-sensing is required, an external current-
sense resistor may optionally be used.
The IC comes in a 28 Ld SSOP package.
Features
• Provides regulated output voltage in the range 0.9V to 5.5V
- High efficiency over wide load range
- Synchronous buck converter with hysteretic operation at
light load
• Complete DDR memory power solution
- VTT tracks VDDQ/2
- VDDQ/2 buffered reference output
• No current-sense resistor required
- Uses MOSFET’s r
DS(ON)
- Optional current-sense resistor for precision overcurrent
• Undervoltage lock-out on VCC pin
• Dual mode operation
- Operates directly from battery 5.0V to 24V input
- Operates from 3.3V or 5V system rail
• Excellent dynamic response
- Combined voltage feed-forward and current mode
control
• Power-good signal for each channel
• 300kHz switching frequency
- Out-of-phase operation for reduced input ripple
- In-phase operation in DDR mode for reduced channel
interference
- Out-of-phase operation with 90° phase shift for
two-stage conversion in DDR mode
• Pb-free plus anneal available (RoHS compliant)
Applications
• Residential and Enterprise Gateways
• DSL Modems
• Routers and Switchers
Ordering Information
PART
NUMBER
ISL6444CA*
PART
MARKING
ISL 6444CA
TEMP.
RANGE
(°C)
PACKAGE
PKG.
DWG. #
-10 to +85 28 Ld QSOP M28.15
ISL6444CAZ* ISL 6444CAZ -10 to +85 28 Ld QSOP M28.15
(Note)
(Pb-free)
*Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN9069 Rev 3.00
Apr 12, 2007
Page 1 of 19
ISL6444
Absolute Maximum Ratings
Bias Voltage, V
cc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
Input Voltage, V
in
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +27.0V
PHASE, BOOT, ISEN, UGATE . . . . . . . . . . . . . GND -0.3V to +33.0V
BOOT with respect to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . .+ 6.5V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V
cc
+ 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1)
JA
(°C/W)
QSOP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
78
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(QSOP - Lead Tips Only)
Recommended Operating Conditions
Bias Voltage, V
cc
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V
5%
Input Voltage, V
in
. . . . . . . . . . . . . . . . . . . . . . . . . . . +5.0V to +24.0V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10°C to +85°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-10°C to +125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
VCC SUPPLY
Bias Current
Shut-Down Current
V
CC
UVLO
Rising V
CC
Threshold
Falling V
CC
Threshold
VIN
Input Voltage Pin Current (Sink)
Input Voltage Pin Current (Source)
Shut-Down Current
OSCILLATOR
PWM1 Oscillator Frequency
Ramp Amplitude, pk-pk
Ramp Amplitude, pk-pk
Ramp Offset
Ramp/V
IN
Gain
Ramp/V
IN
Gain
REFERENCE AND SOFT START
Internal Reference Voltage
Reference Voltage Accuracy
Soft-Start Current During Start-Up
Soft-Start Complete Threshold
PWM CONVERTERS
Load Regulation
VSEN Pin Bias Current
VOUT Pin Input Impedance
Recommended Operating Conditions, Unless Otherwise Noted.
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
CC
I
CCSN
LGATEx, UGATEx Open, VSENx forced above
regulation point, DDR = 0, VIN > 5V
-
-
2.2
-
3.2
30
mA
A
V
CCU
V
CCD
4.3
4.1
4.65
4.35
4.75
4.45
V
V
I
VIN
I
VINO
I
VINS
10
-
-
-
-15
-
30
-30
1
A
A
A
F
c
V
R1
V
R2
V
ROFF
G
RB1
G
RB2
VIN = 16V, by characterization
VIN = 5V, by characterization
By characterization
VIN
3V,
by characterization
1
VIN 3V,
by characterization
255
-
-
-
-
-
300
2
1.25
0.5
125
250
345
-
-
-
-
-
kHz
V
V
V
mV/V
mV/V
V
REF
-
-1.0
0.9
-
-5
1.5
-
+1.0
-
-
V
%
A
V
I
SOFT
V
ST
By characterization
-
-
0.0mA < I
VOUT1
< 5.0A; 5.0V < V
BATT
< 24.0V
I
VSEN
I
VOUT
By characterization
VOUT = 5V
-2.0
50
40
-
80
55
+2.0
120
65
%
nA
k
FN9069 Rev 3.00
Apr 12, 2007
Page 4 of 19
ISL6444
Electrical Specifications
PARAMETER
Undervoltage Shut-Down Level
Overvoltage Shut-Down
GATE DRIVERS
Upper Drive Pull-Up Resistance
Upper Drive Pull-Down Resistance
Lower Drive Pull-Up Resistance
Lower Drive Pull-Down Resistance
POWER GOOD AND CONTROL FUNCTIONS
Power Good Lower Threshold
Power Good Higher Threshold
PGOODx Leakage Current
PGOODx Voltage Low
EN - Low (Off)
EN - High (On)
CCM Enforced (Hysteretic Operation
Inhibited)
Automatic CCM/Hysteretic Operation Enabled
DDR - Low (Off)
DDR - High (On)
DDR REF Output Voltage
DDR REF Output Current
V
DDREF
I
DDREF
DDR = 1, I
REF
= 0...10mA
DDR = 1. Guaranteed by characterization.
VOUTX pulled low
VOUTX connected to the output
V
PG-
V
PG+
I
PGLKG
V
PGOOD
Fraction of the set point; ~3s noise filter
Fraction of the set point; ~3s noise filter.
Guaranteed by characterization.
V
PULLUP
= 5.5V
I
PGOOD
= -4mA
-13
12
-
-
-
2.5
-
0.9
-
2.5
0.99*
V
OC2
-
-
-
-
0.5
-
-
-
-
-
-
V
OC2
10
-7
16
1
0.85
0.8
-
0.1
-
0.8
-
1.01*
V
OC2
16
%
%
A
V
V
V
V
V
V
V
V
mA
R
2UGPUP
R
2UGPDN
R
2LGPUP
R
2LGPDN
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
-
-
-
-
8
3.2
8
1.8
15
5
15
3
Recommended Operating Conditions, Unless Otherwise Noted.
(Continued)
SYMBOL
V
UVL
V
OVP1
TEST CONDITIONS
Fraction of the set point; ~2s noise filter
Fraction of the set point; ~2s noise filter
MIN
70
110
TYP
-
-
MAX
85
130
UNITS
%
%
FN9069 Rev 3.00
Apr 12, 2007
Page 5 of 19
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