High Performance Dual
Ended PWM Controller
POWER MANAGEMENT
Description
The SC4808B-2 is a dual-ended, high frequency, integrated
PWM controller, optimized for isolated applications that
require minimum space. It can be configured for current
or voltage mode operation with required control circuitry
where secondary side error amplifier is used.
Some of the key features are high frequency operation of
1 MHz that allows the use of smaller components thus
saving cost and valuable board space. An internal ramp
on the Current Sense pin allows Internal Slope
Compensation programmed by an external resistor. Other
features include programmable frequency up to 1MHz,
Pulse by Pulse current and Line Monitoring Input with
Hysteresis to reduce stress on the power components.
A unique oscillator is used to synchronize two SC4808B-
2’s to work out of phase. This minimizes the input and
output ripple thus reducing noise on the output line and
reducing stress and size of input/output filter components.
The dual outputs can be configured in Push-Pull, Half Bridge
and Full Bridge format with programmable dead time
between two outputs depending on the size of the timing
components.
The SC4808B-2 also features a turn on threshold of 4.4V
and is available in MSOP-10 package.
SC4808B-2
Features
u
u
u
u
u
u
u
u
u
u
u
u
u
120µA starting current
Pulse by pulse current limit
Programmable operation up to 1MHz
Internal soft start
Programmable line undervoltage lockout
Over current shutdown
Dual output drive stages on push-pull configuration
Programmable internal slope compensation
Programmable mode of operation (peak current mode
or voltage mode)
External frequency synchronization
Bi-phase mode of operation
-40 to 105 °C operating temperature
MSOP-10 Lead-free package. This product is fully WEEE
and RoHS compliant
Telecom equipment and power supplies
Networking power supplies
Industrial power supplies
Push-pull converter
Half bridge converter
Full bridge converter
Isolated VRM’s
Applications
u
u
u
u
u
u
u
Typical Application Circuit
Vo
Vin
Gnd_Out
RSENSE
Gnd_In
OUTA
OUTB
CS
VCC
SYNC
RC
REF
SYNC
FB
LUVLO GND
SC4808
Revision: Dec. 9, 2009
1
www.semtech.com
SC4808B-2
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in
the Electrical Characteristics section is not implied.
Parameter
Supply Voltage
Supply Current
SYNC, RC,CS, LUVLO, REF to GND
FB to GND
REF Current
OUTA/OUTB to GND
OUTA/OUTB Source Current (peak)
OUTA/OUTB Sink Current (peak)
Power Dissipation at T
A
= 25°C
Thermal Resistance
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering) 10 Sec.
ESD Rating (Human Body Model)
Symbol
V
CC
I
CC
Maximum
-0.5 to18
20
-0.5 to 7
Units
V
mA
V
V
mA
V
mA
mA
W
°C/W
°C
°C
°C
kV
V
FB
I
REF
V
OUTA/B
I
source
I
sink
P
D
θ
JA
T
J
T
STG
T
LEAD
V
ESD
-0.5 to (V
REF
+ 0.5)
10
-0.5 to 18
-250
250
1.105
113.1
-40 to 150
-65 to 150
+300
2
Electrical Characteristics
Unless specified: VCC = 12V; CL = 100pF; T
A
= -40°C to 105°C
Parameter
PWM
Maximum Duty Cycle
Minimum Duty Cycle
Current Sense
Gain
Maximum Input Signal
CS to Output Delay
Over Current Threshold
Internal Slope Compensation Resistor
FB to CS Offset
Output
OUT Low Level
OUT High Level
Rise Time
Fall Time
©
2009 Semtech Corp.
Test Conditions
Min
Typ
Max
Unit
Fosc = 50kHz, FB = 5V,
Measured at OUTA or OUTB
Fosc = 50kHz, FB = 1.5V,
Measured at OUTA or OUTB
48
49
50
0
%
%
3
475
525
100
.850
.950
25
1.30
1.50
1.70
1
575
mV
ns
V
kΩ
V
0
11.0
.50
11.25
25
25
.70
12.00
V
V
ns
ns
2
www.semtech.com
SC4808B-2
POWER MANAGEMENT
Pin Descriptions
FB:
The inverting input to the PWM comparator. Stray in-
ductances and parasitic capacitance should be minimized
by utilizing ground planes and correct layout guide lines
(see page 19).
REF:
A 0.1µF or 47nF low ESR capacitor is required and
must be placed right at the pin.
CS:
Current sense input and internal slope compensation
are both provided via the CS pin. The current sense input
from a sense resistor is used for the peak current and
overcurrent comparators. An internal 1 to 3 feed back volt-
age divider provides a 3X amplification of the CS signal.
This is used for comparison to the external error amplifier
signal. If an external resistor is connected from CS to the
current sense resistor, the internal current source will pro-
vide a programmable slope compensation. The value of
the resistor will determine the level of compensation. At
higher compensation levels, voltage mode of operation can
be achieved.
RC:
The oscillator programming pin. The oscillator should
be referenced to a stable reference voltage for an accu-
rate and stable frequency. Only two components are re-
quired to program the oscillator, a resistor (tied to Vref and
RC), and a capacitor (tied to the RC and GND). The follow-
ing formula can be used for a close approximation of the
oscillator frequency.
F
OSC
_
A
≅
1
R
OSC
C
TOT
×
0 .8
F
OSC
_
B
≅
1
R
OSC
C
TOT
×
0 .9
LUVLO:
Line undervoltage lockout pin. An external resis-
tive divider will program the undervoltage lockout level. The
external divider should be referenced to the quiet analog
ground (see page 19). During the LUVLO, the driver out-
puts are disabled and the softstart is reset. This pin can
also function as an Enable/Disable.
SYNC:
SYNC is a positive edge triggered input with a thresh-
old set to 1.0V. In a single controller operation, SYNC could
be grounded or connected to an external synchronization
clock within the SYNC frequency range (see page 3). In
the Bi-Phase operation mode SYNC pins could be con-
nected to the Cosc (Timing Capacitors) of the other con-
troller. This will force an out of phase operation (see page
12).
GND:
Device power and analog ground. Careful attention
should be paid to the layout of the ground planes (see page
19).
OUTA and OUTB:
Out of phase gate drive stages. The
driver’s peak source and sink current drive capability of
100mA, enables the use of an external MOSFET driver or
a NPN/PNP transistor buffer.
The oscillator RC network programs the oscillator frequency,
which is twice the OUTA/OUTB frequency. To insure that
the outputs do not overlap, a dead time can be generated
between the two outputs by sizing the oscillator timing
capacitor (see page 11).
VCC:
The supply input for the device. Once VCC has ex-
ceeded the UVLO limit, the internal reference, oscillator,
drivers and logic are powered up. A low ESR capacitance,
should be used for decoupling right at the IC pin to mini-
mize noise problems.
where:
C
TOT
=
C
OSC
+
C
SC
4808
+
C
Circuit
C
SC
4808
≅
22
pF
Where the frequency is in Hertz, resistance in ohms, and
capacitance in farads. The recommended range of timing
resistors is between 10 kohm and 200kohm and range of
timing capacitors is between 100pF and 1000pF. Timing
resistors less than 10 kohm should be avoided.
Refer to layout guide lines on (page 19) to achieve best
results.
©
2009 Semtech Corp.
5
www.semtech.com
Renesas Electronics MCUs
京公网安备 11010802033920号
EEWORLD
