M39208
Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory
PRELIMINARY DATA
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPARATIONS
100ns ACCESS TIME
(Flash and EEPROM blocks)
WRITE, PROGRAM and ERASE STATUS BITS
CONCURRENT MODE (Read Flash while
writing to EEPROM)
100,000 ERASE/WRITE CYCLES
10 YEARS DATA RETENTION
LOW POWER CONSUMPTION
– Stand-by mode: 60µA
– Automatic Stand-by mode
– Deep Power Down mode
64 bytes ONE TIME PROGRAMMABLE
MEMORY
STANDARD EPROM/OTP MEMORY
PACKAGE
EXTENDED TEMPERATURE RANGES
DESCRIPTION
The M39208 is a memory device combining Flash
and EEPROM into a single chip and using single
supply voltage. The memory is mapped in two
blocks: 2 Mbit of Flash memory and 64 Kbit of
EEPROM memory. Each space is independant for
writing, in concurrent mode the Flash Memory can
be read while the EEPROM is being written.
Table 1. Signal Names
A0-A17
DQ0-DQ7
EE
EF
G
W
V
CC
V
SS
Address Inputs
Data Input / Outputs
TSOP32 (NA)
8 x 20 mm
TSOP32 (NB)
8 x 14 mm
Figure 1. Logic Diagram
VCC
18
A0-A17
W
EE
EF
G
M39208
8
DQ0-DQ7
EEPROM Block Enable
Flash Block Enable
Output Enable
Write Enable
Supply Voltage
Ground
VSS
AI02589
February 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/30
M39208
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9
, V
G
, V
EF
(2)
Parameter
Ambient Operating Temperature
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, G, EF Voltage
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 5
–0.6 to 5
–0.6 to 13.5
Unit
°C
°C
°C
V
V
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
Figure 2. TSOP Pin Connections
A11
A9
A8
A13
A14
A17
W
VCC
EE
A16
A15
A12
A7
A6
A5
A4
1
32
8
9
M39208
25
24
16
17
AI02587
G
A10
EF
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
of the data can be secured with the help of the
Software Data Protection (SDP).
The M39208 Flash Memory block offers 4 sectors
of 64 Kbytes, each sector may be erased individu-
ally, and programmed Byte-by-Byte. Each sector
can be separately protected and unprotected
against program and erase. Sector erasure may be
suspended, while data is read from other sectors
of the Flash memory block (or EEPROM memory
block), and then resumed.
During a Program or Erase cycle in the Flash
memory block or during a Write in the EEPROM
memory block, the status of the M39208 internal
logic can be read on the Data Outputs DQ7,DQ6,
DQ5 and DQ3.
PIN DESCRIPTION
Address Inputs (A0-A17).
The address inputs for
the memory array are latched during a write opera-
tion. A0-A12 access locations in the EEPROM
memory block A0-A17 access locations in the Flash
memory block. The memory block selected is given
by the state on the EE and EF inputs respectively.
When a specific voltage (V
ID
) is applied on the A9
address input, additional specific areas can be
accessed: Read the Manufacturer identifier, Read
the Flash block identifier, Read/Write the EEPROM
block identifier, Verify the Flash Sector Protection
Status.
Data Input/Output (DQ0-DQ7).
A write operation
inputs one byte which is latched when EE (or EF)
and Write Enable W are driven active.
Data read is valid when one Chip Enable (Chip
Enable Flash or Chip Enable EEPROM) and Out-
put Enable are driven active. The output is high
DESCRIPTION
(Cont’d)
An additional 64 bytes of EPROM are One Time
Programmable.
The M39208 EEPROM memory block may be writ-
ten by byte or by page of 64 bytes and the integrity
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M39208
Figure 3. Flash Block Sectors
A17
1
1
0
0
AI02588
A16
1
0
1
0
64K Bytes Block
64K Bytes Block
TOP
ADDRESS
3FFFFh
2FFFFh
1FFFFh
0FFFFh
BOTTOM
ADDRESS
30000h
20000h
10000h
00000h
impedance when the chip is deselected (both EE
and EF driven high) or the outputs are disabled (G
driven high).
Read operations are used to output the contents
from the memory, the Manufacturer identifier, the
Flash Sector protection Status, the Flash block
Identifier, the EEPROM identifier or the OTP row
content.
Memory Block Enable (EE and EF).
The Memory
Block Enable (EE or EF) activates the memory
control logic, input buffers, decoders and sense
amplifiers. When the EE input is driven high, the
EEPROM memory block is not selected; when the
EF input is driven high, the Flash memory block is
not selected. Attempts to access both EEPROM
and Flash blocks (EE low and EF low) are forbid-
den. Switching between the two memory block
enables (EE and EF) must not be made on the
same clock cycle, a delay of greater than t
EHFL
must
be inserted.
The M39208 is in standby when both EF and EE
are High (when no internal Erase or programming
is running). The power consumption is reduced to
the standby level and the outputs are in the high
impedance state, independent of the Output En-
able G or Write Enable W inputs.
After 150ns of inactivity and when the addresses
are driven at CMOS levels, the chip automatically
enters a pseudo standby mode where consumption
is reduced to the CMOS standby value, while the
outputs continue to drive the bus.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. The data outputs are in the high imped-
ance state when the Output Enable G is High.
During Sector Protect and Sector Unprotect opera-
tions, the G input must be forced to V
ID
level (12V
+ 0.5V) (for Flash memory block only).
Write Enable (W).
Addresses are latched on the
falling edge of W, and Data Inputs are latched on
the rising edge of W.
OPERATIONS
The M39208 memory is addressed through 18
inputs A0-A17 and provides data on eight Data
Inputs/Outputs DQ0-DQ7 with the help of four con-
trol lines: Chip Enable EEPROM (EE), Chip Enable
Flash (EF), Output Enable (E) and Write Enable
(W) inputs.
An operation is defined as the basic decoding of
the logic level applied to the control input pins (EF,
EE, G, W) and the specified voltages applied on
the relevant address pins. These operations are
detailed in Table 3.
Read.
Both Chip Enable and Output Enable (that
is EF and G or EE and G) must be low in order to
read the output of the memory.
Read operations are used to output the contents
from the Flash or EEPROM block, the Manufac-
turer identifier, the Flash Sector protection Status,
the Flash block Identifier, the EEPROM identifier or
the OTP row content.
Notes:
– The Chip Enable input mainly provides power
control and should be used for device selection.
The Output Enable input should be used to gate
data onto the output in combination with active
EF or EE input signals.
– The data read depends on the previous instruc-
tion entered into the memory (see Table 4).
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M39208
Table 3. Basic Operations
Operation
Read
EF
V
IL
V
IH
Write
V
IL
V
IH
Output Disable
Standby
Note:
X = V
IL
or V
IH
.
EE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
G
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
X
W
V
IH
V
IH
V
IL
V
IL
X
X
X
DQ0 - DQ7
Read in Flash Block
Read in EEPROM Block
Write in Flash Block
Write in EEPROM Block
Hi-Z
Hi-Z
Hi-Z
V
IL
V
IH
V
IH
Write.
A Write operation can be used for two goals:
– either write data in the EEPROM memory block
– or enter a sequence of bytes composing an
instruction.
The reader should note that Programming a Flash
byte is an instruction (see Instructions paragraph).
Writing data requires:
– the Chip Enable (either EE or EF) to be Low
– the Write Enable (W) to be Low with Output
Enable (G) High.
Addresses in Flash block (or EEPROM block) are
latched on the falling edge of W or EF (EE) which-
ever occurs last; the data to be written in Flash
block (EEPROM block) is latched on the rising edge
of W or EF (EE) whichever occurs first.
Specific Read and Write Operations.
Device
specific data is accessed through operations de-
coding the V
ID
level applied on A9 (V
ID
= 12V +
0.5V) and the logic levels applied on address inputs
(A0, A1, A6). These specific operations are:
– Read the Manufacturer identifier
– Read the Device identifier
– Define the Flash Sector protection
– Read the EEPROM identifier
– Write the EEPROM identifier
Note: The OTP row (64 bytes) is accessed with a
specific software sequence detailed in the para-
graph "Write in OTP row".
Instructions
An instruction is defined as a sequence of specific
Write operations. Each received byte is sequen-
tially decoded (and not executed as standard Write
operations) and the instruction is executed when
the correct number of bytes are properly received
and the time between two consecutive bytes is
shorter than the time-out value.
The sequencing of any instruction must be followed
exactly, any invalid combination of instruction bytes
or time-out between two consecutive bytes will
reset the device logic into a Read memory state
(when addressing the Flash block) or directly de-
coded as a single operation when addressing the
EEPROM block.
The M39208 set of instructions includes:
– Program a byte in the Flash block
– Read a Flash sector protection status
– Erase instructions: Flash Sector Erase, Flash
Block Erase, Flash Sector Erase Suspend, Flash
Sector Erase Resume
– EEPROM power down
– Deep power down
– Set/Reset the EEPROM software write protec-
tion (SDP)
– OTP row access
– Reset and Return
– Read identifiers: read the manufacturer identi-
fier, Read the Flash block identifier
These instructions are detailed in Table 4.
For efficient decoding of the instruction, the two first
bytes of an instruction are the coded cycles and are
followed by a command byte or a confirmation byte.
The coded cycles consist of writing the data AAh at
address 5555h during the first cycle and data 55h
at address 2AAAh during the second cycle.
In the specific case of the Erase instruction, the
instruction expects confirmation by two additional
coded cycles.
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M39208
Table 4. Instructions
(1)
Instruction
Read Manufacturer
Identifier
(2)
EE
EF
Cycle 1
AAh
@5555h
Cycle 2
55h
@2AAAh
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Read
Identifier
90h
with
@5555h
(A0,A1,A6)
at (0,0,0)
Read
identifier
90h
with
@5555h
(A0,A1,A6)
at (1,0,0)
90h
@5555h
Read
byte 1
Read
byte 2
Read
byte N
1
0
Read Flash
Identifier
(2)
1
0
AAh
@5555h
AAh
@5555h
AAh
@5555h
AAh
@5555h
AAh
@5555h
AAh
@5555h
B0h
@any
address
30h
@any
address
AAh
@5555h
20h
@5555h
AAh
@5555h
AAh
@5555h
AAh
@5555h
F0h @
any
address
AAh
@5555h
F0h
@any
address
55h
@2AAAh
55h
@2AAAh
55h
@2AAAh
55h
@2AAAh
55h
@2AAAh
55h
@2AAAh
Read OTP Row
0
1
Read Block
Protection Status
(2)
1
0
Read
Identifier
90h
with
@5555h
(A0,A1,A6)
at (0,1,0)
A0h
@5555h
80h
@5555h
80h
@5555h
Data
@address
AAh
@5555h
AAh
@5555h
55h
@2AAAh
55h
@2AAAh
30h
@Sector
address
10h
@5555h
30h
@Sector
address
(3)
Program a Flash Byte
Erase one Flash
Block
Erase the Whole Flash
Suspend Block Erase
1
1
1
1
0
0
0
0
Resume Block Erase
EEPROM Power
Down
Deep Power Down
SDP Enable
(EEPROM)
SDP Disable
(EEPROM)
Write in OTP Row
Return (from OTP
Read or EEPROM
Power Down)
Reset
Reset (short
instruction)
1
0
1
0
0
0
0
0
1
0
1
1
1
1
55h
@2AAAh
30h
@5555h
55h
@2AAAh
55h
@2AAAh
55h
@2AAAh
A0h
@5555h
80h
@5555h
B0h
@5555h
Write
byte 1
AAh
@5555h
Write
byte 1
Write
byte 2
55h
@2AAAh
Write
byte 2
20h
@5555h
Write
byte N
Write
byte N
1
0
55h
@2AAAh
F0h
@any
Address
1
0
Notes:
1. AAh @5555h means Write byte AAh at address 5555h.
2. This instruction can also be performed as a simple Read operation with A9=V
ID
(refer to READ chapter).
3. Additional blocks to be erased must be entered within 80µs.
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Embedded System
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