BU-62743F3-102L datasheet, PDF

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BU-62743F3-102L: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, 1 INCH, CERAMIC, QFP-72; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，57 Pages; ManufacturerData Device Corporation

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BU-62743F3-102L Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CQFP72, 1 INCH, CERAMIC, QFP-72

BU-62743F3-102L Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Data Device Corporation
Parts packaging code	QFP
package instruction	QFF,
Contacts	72
Reach Compliance Code	compliant
Address bus width	32
boundary scan	NO
Bus compatibility	PCI
maximum clock frequency	20 MHz
letter of agreement	MIL-STD-1553A; MIL-STD-1553B; MIL-STD-1760; STANAG-3838
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	32
JESD-30 code	S-CQFP-F72
JESD-609 code	e0
length	25.4 mm
low power mode	NO
Number of serial I/Os	2
Number of terminals	72
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QFF
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.94 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	25.4 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

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BU-62743/62843/62864

PCI ENHANCED MINIATURE

ADVANCED COMMUNICATION

ENGINE (PCI ENHANCED MINI-ACE®)

Make sure the next

Card you purchase

has...

FEATURES

•

32-Bit/33MHz, 3.3Volt, PCI Target

Interface

•

Fully Integrated 1553A/B Notice 2,

McAir, STANAG 3838 Interface

Terminal

•

Compatible with Enhanced Mini-ACE,

Mini-ACE (Plus) and ACE Generations

•

Choice of:

• RT only with 4K RAM (BU-62743)

• BC/RT/MT with 4K RAM (BU-62843)

• BC/RT/MT with 64K RAM, with RAM

Parity (BU-62864)

•

3.3V Logic

•

5V Transceiver. Available with 1760 or

McAir Compatible Options

•

1.0-inch square, 72-Pin Flatpack /

Formed Gull Lead Ceramic Package

•

Choice of 10, 12, 16, or 20MHz 1553

Clock

•

Highly Autonomous BC with Built-in

Message Sequence Control:

• Frame Scheduling

• Branching

• Asynchronous Message Insertion

• General Purpose Queue

• User-defined Interrupts

•

Advanced RT Functions:

• Global Circular Buffering

• Interrupt Status Queue

• 50% Circular Buffer Rollover

Interrupts

•

Selective Message Monitor or RT/

Monitor

Actual Size:

1.0” Square Package

DESCRIPTION

The PCI Enhanced Mini-ACE family of MIL-STD-1553 terminals pro-

vides a complete interface between a 32-Bit / 33MHz PCI Bus and a

MIL-STD-1553 bus. These terminals integrate dual transceiver, proto-

col logic, and 4K words or 64K words of RAM.

With a 1.0-inch square package, the PCI Enhanced Mini-ACE is

nearly 100% footprint and software compatible with the Enhanced

Mini-ACE, previous generation Mini-ACE (Plus) terminals, and is soft-

ware compatible with the older ACE series.

The PCI portion of the PCI Enhanced Mini-ACE is powered by 3.3V.

The PCI interface is NOT 5V tolerant.

Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, includ-

ing versions incorporating McAir compatible transmitters, is provided.

There is a choice of 10, 12, 16, or 20 MHz 1553 clocks. The BC/RT/

MT versions with 64K words of RAM include built-in RAM parity check-

ing.

BC features include a built-in message sequence control engine, with

a set of 20 instructions. This provides an autonomous means of

implementing multi-frame message scheduling, message retry

schemes, data double buffering, asynchronous message insertion,

and reporting to the host CPU.

The PCI Enhanced Mini-ACE RT offers the choices of single and

circular buffering, along with a global circular buffering option, 50%

rollover interrupt for circular buffers, and an interrupt status queue.

FOR MORE INFORMATION CONTACT:

Data Device Corporation

105 Wilbur Place

Bohemia, New York 11716

631-567-5600 Fax: 631-567-7358

www.ddc-web.com

Technical Support:

1-800-DDC-5757 ext. 7771

2002 Data Device Corporation

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