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IDT70V24S25PFI

Description
Dual-Port SRAM, 4KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Categorystorage    storage   
File Size180KB,22 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V24S25PFI Overview

Dual-Port SRAM, 4KX16, 25ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

IDT70V24S25PFI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instruction14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
Contacts100
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time25 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-PQFP-G100
JESD-609 codee0
length14 mm
memory density65536 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals100
word count4096 words
character code4000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4KX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Encapsulate equivalent codeQFP100,.63SQ,20
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum standby current0.005 A
Minimum standby current3 V
Maximum slew rate0.19 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
HIGH-SPEED 3.3V
4K x 16 DUAL-PORT
STATIC RAM
Features
x
x
x
IDT70V24S/L
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
Low-power operation
– IDT70V24S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V24L
Active: 380mW (typ.)
Standby: 660
µ
W (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
x
x
x
x
x
x
x
x
IDT70V24 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
BUSY
and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/
W
L
UB
L
R/
W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
Control
I/O
0L
-I/O
7L
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
BUSY
(1,2)
BUSY
R
(1,2)
Address
Decoder
12
L
A
11L
A
0L
MEMORY
ARRAY
12
Address
Decoder
A
11R
A
0R
CE
L
OE
L
R/
W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/
W
R
SEM
R
INT
R
(2)
2911 drw 01
M/
S
MARCH 2000
1
DSC-2911/8
©2000 Integrated Device Technology, Inc.
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