3.3 VOLT CMOS SyncBiFIFO
TM
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
IDT72V3622
IDT72V3632
IDT72V3642
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
Memory storage capacity:
IDT72V3622 – 256 x 36 x 2
IDT72V3632 – 512 x 36 x 2
IDT72V3642 – 1,024 x 36 x 2
Supports clock frequencies up to 100 MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA,
and
AFA
flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB,
and
AFB
flags synchronized by CLKB
•
•
•
Select IDT Standard timing (using
EFA, EFB, FFA
and
FFB
flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)
Functionally compatible to the 5V operating IDT723622/723632/
723642
Industrial temperature range (–40
ο
C to +85
ο
C) is available
DESCRIPTION:
The IDT72V3622/72V3632/72V3642 are functionally compatible versions
of the IDT723622/723632/723642, designed to run off a 3.3V supply for
exceptionally low-power consumption. These devices are monolithic, high-
speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which
support clock frequencies up to 100MHz and have read access times as fast
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on
board each chip buffer data in opposite directions. Communication between
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
CSA
W/RA
ENA
MBA
Mail 1
Register
Input
Register
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Output
Register
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
36
Write
Pointer
Read
Pointer
EFB/ORB
AEB
FFA/IRA
AFA
FIFO 1
Status Flag
Logic
FS
0
FS
1
A
0
- A
35
10
Programmable Flag
Offset Registers
FIFO 2
Timing
Mode
FWFT
B
0
- B
35
EFA/ORA
AEA
Status Flag
Logic
Write
Pointer
36
FFB/IRB
AFB
36
Read
Pointer
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
Mail 2
Register
Output
Register
FIFO2,
Mail2
Reset
Logic
Input
Register
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4660 drw 01
MBF2
IDT and the IDT logo are trademark of Integrated Device Technology, Inc SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2001
DSC-4660/5
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox
register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the
IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the
First Word Fall Through mode
(FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the
FWFT
pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/ORB)
and a combined Full/Input Ready Flag (FFA/IRA and
FFB/
IRB). The
EF
and
FF
functions are selected in the IDT Standard mode.
EF
indicates whether or not the FIFO memory is empty.
FF
shows whether the
memory is full or not. The IR and OR functions are selected in the First Word
Fall Through mode. IR indicates whether or not the FIFO has available memory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
PIN CONFIGURATION
NC
NC
V
CC
CLKB
ENB
W/RB
CSB
GND
FFB/IRB
EFB/ORB
AFB
AEB
V
CC
MBF1
MBB
RST2
FS1
GND
FS0
RST1
MBA
MBF2
AEA
AFA
V
CC
EFA/ORA
FFA/IRA
CSA
W/RA
ENA
CLKA
GND
NC
NC
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
*
NC
B
11
B
10
B
9
B
8
B
7
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
NC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
NC
NC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
NC
4660 drw 02
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP (PQ132-1, order code: PQF)
TOP VIEW
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
2
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Each FIFO has a programmable Almost-Empty flag (AEA and
AEB)
and
a programmable Almost-Full flag (AFA and
AFB). AEA
and
AEB
indicate
when a selected number of words remain in the FIFO memory.
AFA
and
AFB
indicate when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA
and
AFB
are two-stage synchronized to the
port clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA
and
AEB
are two-stage synchronized to the port clock that reads data from its array.
Programmable offsets for
AEA, AEB, AFA
and
AFB
are loaded by using
Port A. Three default offset settings are also provided. The
AEA
and
AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the
AFA
and
AFB
threshold can be set at 8, 16 or 64 locations from the full
boundary. All these choices are made using the FS0 and FS1 inputs during
Reset.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3622/72V3632/72V3642 are characterized for operation from
o
0 C to 70
o
C. Industrial temperature range (-40
ο
C to +85
ο
C) is available by
special order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
PIN CONFIGURATION (CONTINUED)
GND
CLKA
ENA
W/RA
CSA
FFA/IRA
EFA/ORA
V
CC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
V
CC
AEB
AFB
EFB/ORB
FFB/IRB
GND
CSB
W/RB
ENB
CLKB
V
CC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
4660 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
3
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
A0-A35
AEA
AEB
AFA
AFB
B0 - B35
CLKA
Name
Port A Data
Port A Almost-
Empty Flag
Port B Almost-
Empty Flag
Port A Almost-
Full Flag
Port B Almost-
Full Flag
Port B Data
Port A Clock
I/O
I/0
O
(Port A)
O
(Port B)
O
(Port A)
O
(Port B)
I/O
I
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
less than or equal to the value in the Almost-Empty A Offset register, X2.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
less than or equal to the value in the Almost-Empty B Offset register, X1.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB.
FFA/IRA, EFA/ORA, AFA,
and
AEA
are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or
coincident to CLKA.
FFB/IRB, EFB/ORB, AFB,
and
AEB
are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
outputs are in the high-impedance state when
CSA
is HIGH.
CSB
must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0- B35 outputs are in the high-impedance state when
CSB
is HIGH.
This is a dual function pin. In the IDT Standard mode, the
EFA
function is selected.
EFA
indicates
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
indicates the presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA
is synchronized
to the LOW-to-HIGH transition of CLKA.
This is a dual function pin. In the IDT Standard mode, the
EFB
function is selected.
EFB
indicates
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on B0-B35 outputs, available for reading.
EFB/ORB
is synchronized to
the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
This is a dual function pin. In the IDT Standard mode, the
FFA
function is selected.
FFA
indicates whether
or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or
not there is space available for writing to the FIFO1 memory.
FFA/IRA
is synchronized to the LOW-to-
HIGH transition of CLKA.
This is a dual function pin. In the IDT Standard mode, the
FFB
function is selected.
FFB
indicates whether
or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or
not there is space available for writing to the FIFO2 memory.
FFB/IRB
is synchronized to the LOW-to-
HIGH transition of CLKB.
This pin selects the timing mode. A HIGH on
FWFT
selects IDT Standard mode, a LOW selects First
Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT
must be static
throughout device operation.
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when
RST1
and
RST2
go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
Description
CLKB
Port B Clock
I
CSA
CSB
EFA/ORA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A Full/
Input Ready
Flag
Port B Full/
Input Ready
Flag
First Word Fall
Through Mode
Flag Offset
Selects
I
I
O
EFB/ORB
O
ENA
ENB
FFA/IRA
I
I
O
FFB/IRB
O
FWFT
I
FS1, FS0
I
4
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFO
TM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONTINUED)
Symbol
MBA
Name
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
I/O
I
Description
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a
LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a
LOW level selects FIFO1 output register data for output.
MBF1
is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while
MBF1
is LOW.
MBF1
is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH.
MBF1
is set HIGH when FIFO1
is reset.
MBF2
is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while
MBF2
is LOW.
MBF2
is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2
is also set HIGH when
FIFO2 is reset.
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while
RST1
is LOW. The LOW-to-HIGH transition of
RST1
latches the status of FS0 and FS1 for
AFA
and
AEB
offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while
RST2
is LOW. The LOW-to-HIGH transition of
RST2
latches the status of FS0 and FS1 for
AFB
and
AEA
offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB
is LOW.
MBB
I
MBF1
O
MBF2
Mail2 Register
Flag
O
RST1
FIFO1 Reset
I
RST2
FIFO2 Reset
I
W/RA
W/RB
Port A Write/
Read Select
Port B Write/
Read Select
I
I
5
FPGA/CPLD
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