IDT71V3556SA100BGG8 datasheet, PDF

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IDT71V3556SA100BGG8: DescriptionZBT SRAM, 128KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119; Categorystorage storage; File Size638KB，28 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71V3556SA100BGG8 Overview

ZBT SRAM, 128KX36, 5ns, CMOS, PBGA119, 14 X 22 MM, ROHS COMPLIANT, PLASTIC, MS-028AA, BGA-119

IDT71V3556SA100BGG8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	5 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e1
length	22 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.36 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.25 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm

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IDT71V3556S/XS

128K x 36, 256K x 18

3.3V Synchronous ZBT SRAMs

IDT71V3558S/XS

3.3V I/O, Burst Counter

IDT71V3556SA/XSA

Pipelined Outputs

IDT71V3558SA/XSA

◆

Features

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 200 MHz (x18)

(3.2 ns Clock-to-Data Access)

Supports high performance system speed - 166 MHz (x36)

(3.5 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V I/O Supply (V

DDQ)

Optional- Boundary Scan JTAG Interface (IEEE 1149.1

compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch

ball grid array (fBGA)

The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-

bit) synchronous SRAMS. They are designed to eliminate dead bus

cycles when turning the bus around between reads and writes, or

writes and reads. Thus, they have been given the name ZBT

, or

Zero Bus Turnaround.

Address and control signals are applied to the SRAM during one

clock cycle, and two cycles later the associated data cycle occurs, be

it read or write.

The IDT71V3556/58 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be

used to disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V3556/58

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

There are three chip enable pins (CE

, CE

) that allow the

user to deselect the device when desired. If any one of these three are

not asserted when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will be

completed. The data bus will tri-state two cycles after chip is deselected

or a write is initiated.

Description

Pin Description Summary

-A

, CE

R/W

CEN

CLK

ADV/LD

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance b urst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

Static

5281 tbl 01

OCTOBER 2010

DSC-5281/11

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