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IDT70V08L20PFG

Description
Dual-Port SRAM, 64KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100
Categorystorage    storage   
File Size175KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

IDT70V08L20PFG Overview

Dual-Port SRAM, 64KX8, 20ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

IDT70V08L20PFG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionLFQFP,
Contacts100
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time20 ns
JESD-30 codeS-PQFP-G100
JESD-609 codee3
length14 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX8
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
HIGH-SPEED 3.3V
64K x 8 DUAL-PORT
STATIC RAM
Features
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20/25/35ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT70V08S/L
IDT70V08 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
(1,2)
I/O
Control
I/O
0-7R
(1,2)
BUSY
L
BUSY
R
64Kx8
MEMORY
ARRAY
70V08
A
15R
A
0R
A
15L
A
0L
Address
Decoder
Address
Decoder
A
15L
A
0L
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
M/S
NOTES:
1.
BUSY
is an input as a Slave (M/S-V
IL
) and an output when it is a Master (M/S-V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
A
15R
A
0R
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3740 drw 01
(1)
MARCH 2004
DSC-3740/6
1
©2004 Integrated Device Technology, Inc.
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