GS882Z18B-11I datasheet, PDF - EEWORLD Datasheet

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GS882Z18B-11I: DescriptionZBT SRAM, 512KX18, 11ns, CMOS, PBGA119, PLASTIC, BGA-119; Categorystorage storage; File Size803KB，34 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS882Z18B-11I Overview

ZBT SRAM, 512KX18, 11ns, CMOS, PBGA119, PLASTIC, BGA-119

GS882Z18B-11I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA, BGA119,7X17,50
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Maximum access time	11 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.22 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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Preliminary

GS882Z18/36B-11/100/80/66

119-Bump BGA

Commercial Temp

Industrial Temp

Features

• 512K x 18 and 256K x 36 configurations

• User-configurable Pipelined and Flow Through mode

• NBT (No Bus Turn Around) functionality allows zero wait

• Read-Write-Read bus utilization

• Fully pin-compatible with both pipelined and flow through

NtRAM™, NoBL™ and ZBT™ SRAMs

• IEEE 1149.1 JTAG-compatible Boundary Scan

• On-chip write parity checking; even or odd selectable

• ZQ mode pin for user selectable high/low output drive

strength.

• x16/x32 mode with on-chip parity encoding and error

detection

• Pin-compatible with 2M, 4M and 16M devices

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleave Burst mode

• Byte write operation (9-bit Bytes)

• 3 chip enable signals for easy depth expansion

• Clock Control, registered, address, data, and control

• ZZ Pin for automatic power-down

• JEDEC-standard 119-Bump BGA package

-11

Pipeline

3-1-1-1

Flow Through

2-1-1-1

Cycle

10 ns

4.5 ns

210 mA

11 ns

15 ns

150 mA

-100

10 ns

4.5 ns

210 mA

12 ns

15 ns

150 mA

-80

12.5 ns

4.8 ns

190 mA

14 ns

15 ns

130 mA

-66

15 ns

5 ns

170 mA

18 ns

20 ns

130 mA

8Mb Pipelined and Flow Through

100 MHz–66 MHz

3.3 V V

Synchronous NBT SRAMs

2.5 V and 3.3 V V

DDQ

Functional Description

The GS882Z818/36B is an 8Mbit Synchronous Static SRAM.

GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other

pipelined read/double late write or flow through read/single

late write SRAMs, allow utilization of all available bus

bandwidth by eliminating the need to insert deselect cycles

when the device is switched from read to write cycles.

Because it is a synchronous device, address, data inputs, and

read/ write control inputs are captured on the rising edge of the

input clock. Burst order control (LBO) must be tied to a power

rail for proper operation. Asynchronous inputs include the

Sleep mode enable (ZZ) and Output Enable. Output Enable can

be used to override the synchronous control of the output

drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising

edge of the clock input. This feature eliminates complex off-

chip write pulse generation required by asynchronous SRAMs

and simplifies input signal timing.

The GS882Z818/36B may be configured by the user to

operate in Pipeline or Flow Through mode. Operating as a

pipelined synchronous device, in addition to the rising-edge-

triggered registers that capture input signals, the device

incorporates a rising-edge-triggered output register. For read

cycles, pipelined SRAM output data is temporarily stored by

the edge-triggered output register during the access cycle and

then released to the output drivers at the next rising edge of

clock.

The GS882Z818/36B is implemented with GSI's high

performance CMOS technology and is available in a JEDEC-

Standard 119-bump BGA package.

Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles

Clock

Address

Read/Write

Flow Through

Data I/O

Pipelined

Data I/O

Rev: 1.15 6/2001

1/34

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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