TSPC603RMGB/T12LC datasheet, PDF

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TSPC603RMGB/T12LC: DescriptionRISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA255, 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255; CategoryThe embedded processor and controller Microcontrollers and processors; File Size636KB，44 Pages; Manufacturere2v technologies

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TSPC603RMGB/T12LC Overview

RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA255, 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255

TSPC603RMGB/T12LC Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	255
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	75 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B255
length	21 mm
low power mode	YES
Number of terminals	255
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Filter level	MIL-STD-883
Maximum seat height	3 mm
speed	266 MHz
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	21 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Features

•

7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (estimated)

Superscalar (3 instructions per clock peak)

Dual 16 KB Caches

Selectable Bus Clock

32-bit Compatibility PowerPC Implementation

On-chip Debug Support

typical = 3.5 Watts (266 MHz), Full Operating Conditions

Nap, Doze and Sleep Modes for Power Savings

Branch Folding

64-bit Data Bus (32-bit Data Bus Option)

4-Gbytes Direct Addressing Range

Pipelined Single/Double Precision Float Unit

IEEE 754 Compatible FPU

IEEE P 1149-1 Test Mode (JTAG/C0P)

INT

max = 300 MHz

BUS

max = 75 MHz

Compatible CMOS Input/TTL Output

Screening/Quality/Packaging

This product is manufactured in full compliance with:

•

CI-CGA 255: MIL-STD-883 class Q or According to ATMEL-Grenoble standards

CBGA 255: Upscreenings based upon ATMEL-Grenoble standards

Full Military Temperature Range (T

= -55°C, T

= +125°C)

IndustriaL Temperature Range (T

= -40°C, T

= +110°C)

Internal/IO Power Supply = 2.5 ± 5% // 3.3V ± 5%

255-lead CBGA Package and 255-lead CBGA with SCI (CI-CGA) Package

PowerPC

603e™ RISC

Microprocessor

Family

PID7t-603e

Specification

TSPC603R

Description

The PID7t-603e implementation of PowerPC 603e (after named 603r) is a low-power

implementation of reduced instruction set computer (RISC) microprocessors Pow-

erPC family. The 603r implements 32-bit effective addresses, integer data types of 8,

16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603r is a low-power 2.5/3.3-volt design and provides four software controllable

power-saving modes.

The 603r is a superscalar processor capable of issuing and retiring as many as three

instructions per clock. Instructions can execute out of order for increased perfor-

mance; however, the 603r makes completion appear sequential. The 603r integrates

five execution units and is able to execute five instructions in parallel.

The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically

addressed caches for instructions and data and on-chip instruction and data Memory

Management Units (MMUs). The MMUs contain 64-entry, two-way set-associative,

data and instruction translation look aside bu ffers that provide suppor t for

demand-paged vir tual memor y address translation and variable-sized block

translation.

The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r

interface protocol allows multiple masters to complete for system resources through a

central external arbiter. The 603r supports single-beat and burst data transfers for

memory accesses, and supports memory-mapped I/O.

Rev. 2125A–HIREL–04/02

TSPC603R

Introduction

The 603r is a low-power implementation of the PowerPC microprocessor family of

reduced instruction set computer (RISC) microprocessors. The 603r implements the

32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses,

integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.

For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer

data types, 64-bit addressing, and other features required to complete the 64-bit

architecture.

The 603r provides four software controllable power-saving modes. Three of the modes

(the nap, doze, and sleep modes) are static in nature, and progressively reduce the

amount of power dissipated by the processor. The fourth is a dynamic power manage-

ment mode that causes the functional units in the 603r to automatically enter a

low-power mode when the functional units are idle without affecting operational perfor-

mance, software execution, or any external hardware.

The 603r is a superscalar processor capable of issuing and retiring as many as three

instructions per clock. Instructions can execute out of order for increased performance;

however, the 603r makes completion appear sequential.

The 603e integrates five execution units — an integer unit (IU), a floating-point unit

(FPU), a branch processing unit (BPU), a load/store unit (LSU) and a system register

unit (SRU). The ability to execute five instructions in parallel and the use of simple

instructions with rapid execution times yield high efficiency and throughput for

603r-based systems. Most integer instructions execute in one clock cycle. The FPU is

pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603r provides independent on-chip, 16-Kbyte, four-way set-associative, physically

addressed caches for instructions and data and on-chip instruction and data memory

management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data

and instruction translation look aside buffers (DTLB and ITLB) that provide support for

demand-paged virtual memory address translation and variable-sized block translation.

The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603r

also supports block address translation through the use of two independent instruction

and data block address translation (IBAT and DBAT) arrays of four entries each. Effec-

tive addresses are compared simultaneously with all four entries in the BAT array during

block translation. In accordance with the PowerPC architecture, if an effective address

hits in both the TLB and BAT array, the BAT translation takes priority.

The 603r has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603r

interface protocol allows multiple masters to compete for system resources through a

central external arbiter. The 603r provides a three-state coherency protocol that sup-

ports the exclusive, modified, and invalid cache states. This protocol as a compatible

subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates

coherently in systems that contain four-state caches. The 603r supports single-beat and

burst data transfers for memory accesses, and supports memory-mapped I/O.

The 603r uses an advanced, 0.29 µm 5 metal layer CMOS process technology and

maintains full interface compatibility with TTL devices.

2125A–HIREL–04/02

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