78P2342-IGT/A07 datasheet, PDF

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78P2342-IGT/A07: DescriptionTelecom IC, PQFP100,; CategoryWireless rf/communication Telecom circuit; File Size340KB，36 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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78P2342-IGT/A07 Overview

Telecom IC, PQFP100,

78P2342-IGT/A07 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	QFP
Contacts	100
Reach Compliance Code	not_compliant
Carrier type	E-3
Carrier Type (2)	STS-1/OC-1
Carrier type (3)	T-3(DS3)
JESD-30 code	S-PQFP-G100
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	187 mA
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD

78P2342-IGT/A07 Preview

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

DATA SHEET

JULY 2005

DESCRIPTION

The 78P2342JAT is a low-power, 2-port

DS3/E3/STS1 Line Interface Unit (LIU) with

integrated Jitter Attenuator (JAT). It includes all the

required clock recovery and transmitter pulse

shaping functions for applications using 75-ohm

coaxial cable at distances up to 1350 feet. These

applications include DSLAMs, T1,3/E1,3 digital

multiplexers, SONET Add/Drop multiplexers, PDH

equipment, DS3 to Fiber optic and microwave

modems and ATM WAN access for routers and

switches.

The receiver recovers clock and data from a B3ZS

or HDB3 coded AMI signal. It can compensate for

over 12dB of cable and 6dB of flat loss. The

transmitter generates a signal that meets the

standard pulse shape requirements.

The

78P2342JAT includes optional B3ZS/HDB3 ENDEC

with a receive line code violation detector, loop-back

modes, Loss of Signal detector, clock polarity

selection, and the ability to receive a DSX3 monitor

signal.

FEATURES

•

Transmit and receive interfaces for E3, DS3 and

STS-1 applications

Designed for use with 75 ohm coaxial cable

lengths up to 1350 ft

Receives DS3-high and DSX3 monitor signals

Local and Remote loopbacks

Selectable B3ZS/HDB3 ENDEC with line code

violation detector

Standards-based LOS detector

Optional serial-port based mode selection and

channel status monitoring

Adaptive digital clock recovery (uses line-rate

reference clock input)

Receive output clock maintains nominal line-rate

frequency at all times

Fully integrated Jitter Attenuation function

provided for all line rates (no external VCXO

required)

Jitter Attenuator configurable for transmit or

receive path

Transmit line fault monitor

Requires no external current-setting resistor or

loop filter components

Single 3.3V supply operation

Available in a standard 100-pin JEDEC LQFP

STANDARDS

•

Telcordia GR-499-CORE and GR-253-CORE

ITU-T G.823, G.824, G.775, and G.703

ETSI TBR-24, ETS 300 686, ETS 300 687, and

ETS EN 300 689

ANSI T1.102-1993, T1.231-1997, T1.404-1994,

and T1.105.03b

BLOCK DIAGRAM

Controls

Flags

RLBK

LBO E3 DS3

TXEN

TPOS

TNEG

TCLK

Jitter

Attenuator

RPOS

RNEG

RCLK

B3ZS /

HDB3

Decoder

B3ZS /

HDB3

Encoder

Transmit

Monitor

TXNW

Pulse

Shaper

LOUTP

LOUTN

Attenuator

ENDEC

Data

Detector

Adaptive

Equalizer

AGC

LINP

LINN

MON

TCLKP

RCLKP

Power

Distribution

Clock

Recovery

Signal

Detector

LLBKA

LLBKB

Signals from

Adjacent Port

LOS

PDTX PDRX

CKREF

Each Channel

SCK

SDI

SDO

Control

Registers

Master

Bias

Generator

CKREF

Page 1 of 36



2005 Teridian Semiconductor Corporation

Rev 2.2

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

FUNCTIONAL DESCRIPTION

The 78P2342JAT contains all the necessary

transmit and receive circuitry for connection

between E3, DS3, or STS-1 line interfaces and

digital Framer/Mapper ICs.

OPERATING RATE

The Master Control Register (MSCR) determines

which mode the device operates in according to the

table below. The MSL0 pin is also provided for

mode selection in applications without a serial

control interface. Upon power-up or reset, the state

of the MSL0 pin is sensed and mapped into the DS3

and E3 register bits representing the appropriate

mode of operation. After power-up/reset, the state of

the MSL0 pin is ignored.

Standard

DS3

STS-1

MSL0 pin

DS3 bit

E3 bit

The jitter tolerance of 78P2342JAT meets the

requirements of ITU-T G.823 for E3 rates; the

requirements of ITU-T G.824 and Telcordia GR-499

(Cat I and II) for DS3 rates; and the requirements of

Telcordia GR-253 for STS1 rates.

With the Jitter Attenuator disabled, the jitter transfer

function meets the requirements of GR-499 for

Category II DS3 interfaces.

When the Jitter Attenuator is enabled, the

78P2342JAT meets the requirements of GR-499

and GR-253 for all categories of DS3/STS1

equipment and the ETSI TBR-24 requirements for

E3 rates.

To check conformance with other

standards,

please

refer

the

JITTER

ATTENUATOR TRANSFER FUNCTION section for

more detailed info.

RECEIVER MONITOR MODE

When in monitor mode, 20dB of flat gain is applied

to the incoming signal before it is fed to the receive

equalizer. This mode is controlled by the MON bit in

the Mode Control Register.

SIGNAL DETECT

When the received signal is below a minimum

threshold, the corresponding LOS signal (bit) is

asserted. A time delay is provided before this output

is active so that transient interruptions do not cause

false indications. The LOS signal can also be used

to trigger an interrupt on the INTRx pin when serial

interface control is not available. This is controlled

by setting the RXER bit in the Interrupt Control

Note: In DS3 or STS-1 mode, when LBO is not

enabled, the transmitters have to be properly

terminated to ensure reliable LOS detection. If a

transmitter is not terminated, the resultant 2x signal

is large enough to couple to the neighboring

receivers through the ESD diodes, causing false

Signal Detect indication.

RECEIVER OPERATION

The receiver input is either transformer-coupled or

capacitor-coupled to the line signal. In applications

where the highest performance and isolation are

required, a 1:1 transformer is used in the receive

path. In applications where isolation is provided

elsewhere in the circuit, capacitor coupling can be

used. The receiver input should be line terminated

externally with a termination resistor.

The AMI signal first enters an AGC, which has a

selectable gain range setting. In normal operation,

the AGC can compensate for signals with up to 6dB

of flat loss. When Receiver Monitor Mode is

enabled, the AGC can compensate for a DSX3

monitor signal with 16 to 20 dB of flat loss. The

signal then enters a high performance adaptive

equalizer. The equalizer is designed to overcome

inter-symbol interference caused by long cable

lengths. Because the equalizer is adaptive, the

circuit will work with all square-shaped signals such

as DS3-high or 34.368 Mbit/s E3. The variable gain

differential amplifier automatically controls the gain

to maintain a constant voltage level output

regardless of the input voltage level.

Page 2 of 36



2005 Teridian Semiconductor Corporation

Rev 2.2

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

LOCAL LOOPBACK AND REDUNDANCY MUX

Each receiver has a 4-input MUX as shown in the

adjacent figure. In multiport applications where

redundant channels are required, the receiver MUX

can be configured to provide the necessary

multiplexing functions. This allows the user to use

one port as a redundant monitor for the other port.

The tables below show the register settings for

selecting the desired receiver input source.

LLBKA

(Port 1)

LLBKA

(Port 2)

LLBKB

(Port 1)

LLBKB

(Port 2)

Receiver #1 Input

Source

LINP1/LINN1

LOUTP1/LOUTN1

LINP2/LINN2

LOUTP2/LOUTN2

Receiver #2 Input

Source

LINP2/LINN2

LOUTP2/LOUTN2

LINP1/LINN1

LOUTP1/LOUTN1

LOUTP1, LOUTN1

Transmitter

LINP1, LINN1

Receiver

LLBKA,B(1)

LOUTP2, LOUTN2

Transmitter

LINP2, LINN2

Receiver

LLBKA,B(2)

When serial interface control is not available, the

respective LPBKx pin for each of the channels can

also be used to activate local loopback mode as

shown below. Note that redundant channel modes

can only be activated using the serial interface.

LPBKx

Loopback Mode

Normal Operation

Same as LLBKA,B = ‘00’

Remote (Digital) Loopback

Same as RLBK = ‘1’

Local (Analog) Loopback

Same as LLBKA,B = ‘01’

Note: The LLBKA and LLBKB bits are located in the

Mode Control Register (MDCR).

The Register

Control bit, REGEN, should be enabled when using

the register settings to avoid conflict with external

loopback setting pins.

Page 3 of 36



2005 Teridian Semiconductor Corporation

Rev 2.2

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

B3ZS/HDB3 ENDEC WITH LINE CODE VIOLATION

DETECT

The 78P2342JAT includes a selectable B3ZS/HDB3

Encoder/Decoder (ENDEC). The ENDEC function

can be enabled or disabled through pin selection or

ENDECB

bit/pin

0/L

1/H

RPOSx

NRZ data

Positive AMI

RNEGx

Receive Line Code

Violation Indicator

Negative AMI

On the transmit side, when the ENDEC is enabled,

NRZ input data is encoded to Positive and Negative

AMI logic data following the B3ZS (for DS3/STS-1)

or HDB3 (for E3) substitution codes. The NRZ data

is input to the TPOS pin as shown below:

ENDECB

bit/pin

0/L

1/H

TPOSx

NRZ data

Positive AMI

TNEGx

‘Don’t Care’

Negative AMI

TRANSMITTER OPERATION

Both transmitters are enabled by their corresponding

TXEN bit. When enabled, each transmitter accepts

logic level clock and data signals and generates

current pulses on the LOUTPx and LOUTNx pins.

When properly connected to a 1:2CT center-tapped

transformer, a standards compliant AMI pulse is

generated which can drive a 75

Ω

coaxial cable.

When the recommended transformer is used and

when DS3 mode is selected, the transmitted pulse

shape at the end of the 75

Ω

terminated cable of 0 to

450 feet will fit the DS3 template in ANSI T1.102-

1993 and Telcordia GR-499-CORE. For STS-1

applications, the transmitted pulse for a short cable

meets the requirements of Telcordia GR-253-CORE.

For E3 applications, the transmitted pulse for a short

cable meets the requirements of ITU-T G.703.

In either DS3 and STS-1 modes, the LBOx pin or

LBO bit should be set high for short cable (< 225 ft),

and should be set low for long cable (> 225 ft). The

LBO settings are ignored in E3 mode.

RCLK/TCLK POLARITY REVERSAL

To simplify the interface with various framer circuitry,

TCLK polarity can be internally inverted by setting

the TCLKP bit, and RCLK polarity can be inverted

by setting the RCLKP bit. Both bits are located in

the Master Control Register (MSCR).

REMOTE (DIGITAL) LOOPBACK

When the Register Control bit, REGEN, is disabled

and the LPBKx pin is floating; or when the Register

Control bit, REGEN, is enabled and the RLBK bit is

set, RCLKx, RNEGx, and RPOSx outputs are

internally looped back to the TCLKx, TNEGx, and

TPOSx inputs respectively.

When the ENDEC is enabled, the decoder

generates a composite NRZ logic data stream

following the B3ZS (for DS3/STS-1) or HDB3 (for E3)

substitution codes via the RPOSx pins:

The decoder also detects Receive Line Code

Violations (RLCV) and outputs a pulse via the

RNEG pin. Three different classes of line code

violations are detected.

1) Too many zeros:

More than two (three)

consecutive zeros in B3ZS (HDB3) mode.

2) Not enough zeros between bipolar pulse (B)

and bipolar violation pulse (V): (B,V) for B3ZS.

(B,V) or (B,0,V) for HDB3.

3) Code violation: Even number of bipolar pulses

(B) detected between bipolar violation pulses

(V).

When the ENDEC is disabled, the 78P2342JAT

outputs a dual rail data stream via the RPOSx and

RNEGx pins. In this mode, the Framer/Mapper

providing the ENDEC function typically detects Line

Code Violations.

Page 4 of 36



2005 Teridian Semiconductor Corporation

Rev 2.2

78P2342JAT

2-port E3/DS3/STS-1 LIU

with Jitter Attenuator

LINE BUILD-OUT

The Line Build-Out (LBO) function controls the

transmit amplitude and pulse shape in DS3 and

STS-1 modes. The selection of LBO depends on

the amount of cable the transmitter is connected to.

When less than 225 ft of cable is used, the

corresponding LBOx pin or LBO bit should be high.

When 225ft or more cable is used the corresponding

LBO setting (LBOx pin or LBO bit) should be low.

LBO can be controlled either from pins or from

TRANSMIT ENABLE

The TXEN bit in the Mode Control Register controls

the transmitter output.

When logic zero, the

transmitter output is disabled. This feature is used to

disable ports as well as to multiplex two or more

transceivers to one port. The transmitter of any port

can also be disabled by floating the respective LBOx

pin, in which case it will also power-down the entire

transmitter.

See section on the Power-Down

Function for more info.

TRANSMIT MONITOR

The transmit monitor function detects activity on the

transmitter output at the LOUTPx and LOUTNx pins.

When there is a transmitter fault, in the case of an

open or short on the chip, the transformer, or the

circuit board, the transmit signal amplitude will be

altered. The transmit monitor detects the amplitude

of the driven signal. The TXNW signal (bit) goes

high when the amplitude of the transmit signal is

outside a valid amplitude range. When the signal

amplitude is either too high or too low for longer than

a specified duration, the TXNW bit goes high (See

Transmit Monitor Specifications, pg.28). The TXNW

signal can be also used to trigger an interrupt on the

INTRx pin when serial interface control is not

available.

JITTER ATTENUATOR

Jitter Attenuation function is provided on-chip. The

Jitter Attenuator can be configured to be in the

transmit or the receive path. When configured in the

transmit path, the input clock at TCLK pin is passed

through a very low bandwidth digital PLL. The

corresponding transmit data is buffered into a FIFO

and clocked out using the de-jittered output clock of

the PLL. When configured in the receive path, the

recovered clock is passed through the low

bandwidth digital PLL, and the corresponding

receive data is buffered into the FIFO and clocked

out using the de-jittered clock.

When serial interface control is not available, the

MSL1 pin is provided for global Jitter Attenuator

mode selection. Upon power-up or reset, the state

of the MSL1 pin is sensed and mapped into the

JAEN and JASL register bits for all channels,

representing the appropriate mode of operation.

After power-up or reset, the state of the MSL1 pin is

ignored. The state of the MSL1 pin, and the

corresponding Jitter Attenuator configuration is

shown below.

MSL1 pin

PLL Bandwidth

A PLL response with effectively one pole below 27

Hz is adequate to meet the ETSI TBR24 E3

standards. A PLL response with one pole below 40

Hz is adequate to meet the GR-499 (Cat I) DS3

standards. One of two bandwidths can be selected

via register settings.

The PLL bandwidth is

proportional to the data rate as follows:

Line Rate

DS3

STS1

JABW bit

PLL Bandwidth

(Hz)

*13

188

*17

245

*283

Jitter Attenuator Mode

Jitter Attenuator in receive path

Jitter Attenuator in transmit path

Jitter Attenuator disabled

The Jitter Attenuator can be configured

independently for each channel by writing to the

Jitter Attenuator Control Register (JACR) as follows:

JAEN

bit

JASL

bit

Jitter Attenuator Mode

Jitter Attenuator disabled

Jitter Attenuator configured

to be in the receive path

Jitter Attenuator configured

to be in the transmit path

*The default state of the JABW bit depends on

which line-rate is selected through the MSL0 pin. If

E3 or DS3 mode is selected, the default state is ‘0’.

If STS1 mode is selected, the default state is ‘1’.

Rev 2.2

Page 5 of 36



2005 Teridian Semiconductor Corporation

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