SD-15900
TWO-SPEED S/D OR R/D COMBINER
CONVERTER
DESCRIPTION
The two-speed combiner is designed
to work in conjunction with any two
synchro-to-digital (S/D) or resolver-to-
digital (R/D) converters such as
DDC’s two-channel SD-14620 Series
or two RDC-19220 Series. These
combinations provide a complete
solution to implement two-speed S/D
or R/D conversion.
The SD-14620 Series is a small, low-
cost two-channel hybrid S/D or R/D
converter based on a single chip
monolithic. It features a velocity out-
put, which can be used to replace a
tachometer, and Built-In-Test (BIT).
The RDC-19220 Series is a single
channel monolithic S/D or R/D con-
verter. It also features a velocity out-
put, which can be used to replace a
tachometer, and Built-In-Test (BIT).
The SD-15900 is a digital device
which combines the S/D or R/D digital
information from a coarse channel
and a fine channel to provide up to 22
bits of angular data.
The SD-15900 is set at the factory to
accept a 1 x 36 speed combination.
The combiner, as well as DDC’s
SD-14620 Series and RDC-19220
Series converters, can be powered
from the same +5 V dc power supply.
Please note that if you are using the
RDC-19220 Series, velocity scaling
components are necessary for the
device to function.
FEATURES
•
Single
+5 V Power Supply
•
Resolution of up to 22 Bits
•
Small Size
•
Speed Ratios of: 1 x 4, 8,
16, 18, 32, 36, 64 or 72
APPLICATIONS
The small-size components and the
high accuracy obtainable in two-speed
combination make the SD-15900 ideal
for use in modern, high-performance
military and industrial position control
systems. Typical applications include
radar antenna positioning, navigation
and fire control systems, motor control
and robotics.
Course
Input
Input
Latch
Digital
Combiner
Fine
Input
Input
Latch
Scaler
HOLD
INH
COURSE
FINEHI
FINELO
Timing and
Control
22 Bit
Output
Tri-State
Output
ENHIGH
ENMID
ENLOW
FIGURE 1. SD-15900 BLOCK DIAGRAM
©
1996, 1999 Data Device Corporation
TABLE 1. SD-15900 SPECIFICATIONS
PARAMETER
Absolute Maximum
Ratings
DC Supply Voltage (Vcc)
Input Voltage
Output Voltage
I/O Sink/Source Current
(See NOTE)
Resolution
1
1 x 36
Accuracy (Electrical)
SD-15900 alone
Digital Input/Output
Logic Type
Inputs
V
V
UNIT
VALUE
THEORY OF OPERATION
The two-speed synchro/resolver combiner is a completely self-
contained, real time, mathematically-based processing device.
The combiner accepts two-speed course/fine synchro/resolver
binary angular information from any two S/D converters such as
DDC’s RDC-19220 Series or the two-channel SD-14620 Series
and generates a composite binary angular output word up to 22
bits. All of the required timing and control signals for the two
external synchro/resolver converters are generated by the SD-
15900.
V
V
V
mA
-0.5 to +7.0
-0.5 to Vcc + 0.5
-0.5 to Vcc + 0.5
± 20
Number of bits based on a
16-bit resolution of fine
S/D channel (up to 21 bits).
1.39
TTL/CMOS compatible
Logic 0 = -0.3 min to
0.8 max
Logic 1 = 2.0 min to
power supply
+0.3 max
Logic 0 = 0.5 max
@ 10 mA
Logic 1 = 2.4 min
@ -10 mA
Logic 0 = 0.4 max
@ 6 mA
Logic 1 = 3.7 min
@-4 mA
10
(Output = 0 V, F = 1 MHz)
±10 max
Total Device
+5
5
20 (max)
Bits
COMBINER OPERATION
LSB
FIGURE 1 is the functional block diagram of the SD-15900
series. The combiner is made up of three main sections: an input
front-end, a high resolution digital scaler, and timing and control.
The front-end consists of an Input Latch for both course and fine
data inputs, and a Digital Combiner with misalignment detection
and correction. Course and fine data are presented to the
Combiner via input port IN<1:8>. The fine data word is loaded
as two separate bytes. Control signals COURSE, FINELO, and
FINEHI are used to strobe in the data. The input data is then
latched and combined into a single word. Misalignment between
the course and fine input data is detected at this point and the
course corrected.
NOTE: The maximum detected misalignment will depend on the
target combiner speed ratio. Refer to TABLE 2.
Outputs
-30X
V
V
-10X
V
V
I/O Capacitance
pF
Leakage Current
Power Supplies
Nominal Voltage
Voltage Tolerance
Static Current (IDD)
Temperature Range
Operating
-30X
-10X
Storage
Physical Characteristics
Size
-30X
µA
V
±%
mA
TABLE 2. MISALIGNMENT VS. SPEED RATIO
SPEED RATIO
72 - 63 x 1
62 - 33 x 1
32 - 17 x 1
16 - 9 x 1
8-5x1
4-3x1
MAXIMUM MISALIGNMENT
1.25 degrees
2.5 degrees
5.625 degrees
11.25 degrees
22.5 degrees
45.0 degrees
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
in
(mm)
in
(mm)
ozs
(grams)
1.195 x 1.195 x0.185
(30.35 x 30.35 x 4.70)
1.12 x 1.12 x 0.110
(28.45 x 28.45 x 2.79)
0.32
(9)
-10X
Weight
NOTE:
The device inputs are normally high impedance and
draw extremely low current. However, when input voltage is
greater than Vcc + 0.5 V or less than GND - 0.5V, the inter-
nal protection diode will be forward biased and can draw
excessive current.
1. Please contact factory for other ratios.
The Digital Combiner output is then rescaled by the Scaler and
made available to the outputs. The output port, OUT<1:22>, can
be read by an external device as a single word or as individual
bytes via control input signals ENHIGH, ENMID, and ENLOW.
The outputs are tri-state, allowing “logical-oring” of the individual
bytes for interface to 8-bit devices.
The Timing and Control section defines all of the timing and is
responsible for generating all of the output control signals as well
as the internal data strobes used to latch the input data. An
internal clock can be used for all timing by strapping CLKOUT to
CLKIN, or an external clock can be used by driving input CLKIN.
2
INTERFACING
FIGURE 2 shows a typical application using an SD-14620
Synchro/Resolver-to-Digital Converter and an SD-15900.
The eight Most Significant Bits (MSB’s) of angular information
from the course synchro/resolver converter, along with the eight
Most Significant Bits and eight Least Significant Bits (LSB’s) of
the fine converter are wired together as an 8-bit data bus, and
are connected to the 8-bit data bus input of the code converter
SD-15900.
The Inhibit (INH) signal from the combiner is connected to both
the fine and course synchro/resolver converters Inhibit inputs.
The three Enable signals (COURSE, FINEHI, FINELO) from the
combiner are connected to the associated Enable pins on the
synchro/resolver converters, i.e., Enable Course MSB’s, Enable
Fine MSB’s, and Enable Fine LSB’s.
The Hold input to the combiner can be driven by user-designed
circuitry if it is necessary to momentarily freeze the angular infor-
mation from the combiner based on the specific application.
The CLKOUT of the combiner generates a free running clock of
approximately 8 MHz and can be connected to the CLKIN of the
combiner for stand alone self clocking applications. The CLKIN
is divided by eight to create the internal clock. If it is necessary
to synchronize the clock of the combiner with a user clock, the
user clock can be connected to the CLKIN of the combiner
instead of the combiner-generated CLKOUT. The stability of the
clock is not important to the combiner circuitry and is used only
to set the rate at which the combiner samples the data from the
two synchro/resolver converters. Sampling of the angular data
from the two synchro/resolver converters occurs at the internal
clock rate divided by eight.
COURSE
S1 ch.A
S2 ch.A
S3 ch.A
S4 ch.A
RH ch.A
RL ch.A
S1 ch.B
BITS 1..16
IN<1..8>
OUT <1..16>
+5V
VPP
VCC
HOLD
RES_L
ENHIGH
ENLOW
ENMID
INH
COURSE
FINEHI
FINELO
CLKOUT
FINE
S2 ch.B
S3 ch.B
S4 ch.B
RH ch.B
RL ch.B
SD-15900
SD-14620
INH
EMA
EMB
ELB
MODE
GND
CLKIN
FIGURE 2. SD-15900 TYPICAL APPLICATION
3
INHIBIT AND ENABLE TIMING
FIGURE 3 shows the timing relationships for the SD-15900.
The internal clock is generated in the combiner for the purpose
of running the internal state generator that controls the timing
and control of the circuitry. The frequency of this clock was cho-
sen to be approximately 1 MHz and it is not critical. The top line
of the timing diagram shows the relationship of the clock to the
remaining signals.
The second signal on the timing diagram shows the INH signal
going to the S/D converter. Every eight clock cycles this signal
will go low and inhibit the converter so that the current angles
can be extracted.
The Course MSB’s Enable will be asserted approximately 0.5 µs
after the inhibit is asserted and the associated data is strobed
into the combiner at the mid-point of the enable (approximately
0.5 µs after it goes low). The enable line is then raised back to
logic high.
The fine MSB’s Enable is asserted next and the data is similarly
loaded into the combiner.
The fine LSB’s Enable is then asserted and the associated data
is made available to the combiner. At the rising edge of the fine
LSB’s strobe the two previously loaded angular data values, as
well as the current LSB data is simultaneously transferred to the
input of the internal combining circuitry, and the resulting angle
is generated.
The resulting combined bits of angular data is then made avail-
able via three sets of tri-state buffers; the eight MSB’s, the eight
middle bits, and the six LSB’s. Each set of bits has its own sep-
arate enable line.
The Hold signal on the combiner allows the currently generated
angle to be frozen. The state of the Hold signal is sampled on
the rising edge of every clock cycle. If the sampled signal is high
the transfer of the angular data to the combining circuit will take
place as described above. If the sampled signal is low the data
transfer will be inhibited and the output angle will not be updat-
ed. Data will be valid 0.5 µs after the next rising edge of the inter-
nal clock. This condition will persist until the Hold signal is
brought back to the high state.
The only time the angular output data from the combiner can
change is during the Fine LSB’s Strobe and Data Transfer time.
The settling time during this interval will be limited to a period of
approximately 0.5 µs.
1 µs
INTERNAL CLOCK
INHIBIT
ENABLE COURSE MSB'
S
0.5 µs
COURSE MSB'
S
STROBE
ENABLE FINE MSB'
S
FINE MSB'
S
STROBE
ENABLE FINE LSB'
S
FINE LSB'
S
STROBE
AND DATA TRANSFER
FIGURE 3. SD-15900 TIMING DIAGRAM
4
TABLE 3. SD-15900 SIGNAL FUNCTIONS
PIN
IN<1:8>
DESCRIPTION
Digital input for course and fine data.
(NOTE: Bit 1 is the Most
Significant Bit).
Output data word. (NOTE: Bit 1 is the
Most Significant Bit).
Active low output indicating combiner
output word is NOT ready.
Active low input to the combiner indicat-
ing that external device is busy reading
combiner outputs and that internal data
should be held steady.
Active low output used to enable exter-
nal device output drivers for course byte
data.
Active low output used to enable exter-
nal device output drivers for fine high
byte.
Active low output used to enable exter-
nal device output drivers for fine low
byte data.
Active low input used to enable the
most significant byte of the output word.
Active low input used to enable the mid-
dle byte of the output word.
Active low input used to enable the
least significant byte of the output
word.
Output used to select internal clock by
strapping to CLKIN.
Clock input. Can use internal clock by
strapping CLKOUT to CLKIN.
Used for internal diagnostics. This must
be tied to circuit ground for normal
operation.
Used for device programming. This pin
must be tied to circuit VCC (digital +5V
supply) for normal operation.
Reset Line (Low = Reset); Tie high for
nomal operation.
A1
B1
C1
D1
E1
F1
G1
H1
J1
K1
L1
A2
B2
C2
D2
E2
F2
G2
H2
J2
K2
L2
A3
B3
C3
E3
F3
G3
K3
L3
A4
B4
K4
L4
A5
B5
C5
J5
K5
L5
TABLE 4. PINOUTS
(CERAMIC PGA - FIGURE 4)
PIN FUNCTION PIN FUNCTION
HOLD
IN<1>
IN<2>
IN<3>
IN<4>
V
CC
IN<5>
IN<6>
IN<7>
IN<8>
INH
RES_L
NC
NC
NC
GND
NC
V
CC
NC
NC
V
PP
NC
NC
NC
NC
GND
NC
NC
COURSE
NC
NC
NC
FINEHI
FINELO
NC
V
CC
NC
NC
GND
CLKOUT
A6
B6
C6
J6
K6
L6
A7
B7
C7
J7
K7
L7
A8
B8
K8
L8
A9
B9
E9
F9
G9
K9
L9
ENLOW
NC
NC
NC
NC
CLKIN
ENMID
GND
NC
NC
V
CC
NC
ENHIGH
OUT<3>
OUT<15>
OUT<19>
OUT<1>
OUT<4>
V
CC
NC
OUT<9>
OUT<16>
OUT<20>
TABLE 5. PINOUTS
(PLASTIC J-LEAD - FIGURE 5)
PIN FUNCTION PIN FUNCTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
HOLD
NC
NC
V
CC
NC
NC
NC
NC
NC
NC
NC
NC
IN<1>
IN<2>
IN<3>
IN<4>
IN<5>
GND
GND
IN<6>
IN<7>
IN<8>
INH
COURSE
V
CC
V
CC
FINEHI
FINELO
NC
NC
NC
NC
V
PP
NC
NC
NC
NC
NC
NC
GND
NC
CLKOUT
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLKIN
RES_L
NC
V
CC
ENHIGH
ENMID
ENLOW
OUT<22>
OUT<21>
OUT<20>
OUT<19>
OUT<18>
OUT<17>
OUT<16>
OUT<15>
OUT<14>
OUT<13>
GND
GND
OUT<12>
OUT<11>
NC
OUT<10>
MODE
V
CC
V
CC
OUT<9>
OUT<8>
OUT<7>
NC
NC
NC
NC
OUT<6>
OUT<5>
OUT<4>
OUT<3>
OUT<2>
OUT<1>
GND
NC
NC
OUT<1:22>
INH
HOLD
COURSE
FINEHI
FINELO
ENHIGH
ENMID
ENLOW
CLKOUT
CLKIN
MODE
A10 OUT<2>
B10 NC
C10 NC
D10 OUT<6>
E10 V
CC
F10 GND
G10 GND
H10 OUT<11>
J10
OUT<13>
VPP
RES_L
K10 OUT<17>
L10 OUT<21>
A11 NC
B11 NC
C11 OUT<5>
D11 OUT<7>
E11 MODE
F11 OUT<8>
G11 OUT<10>
K11 OUT<18>
H11 OUT<12>
J11 OUT<14>
L11 OUT<22>
5
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